OSPI x1 Configuration Interface Example - OSPI x1 Configuration Interface Example - UG860

See the following figure for the octal SPI interface connectivity.

Figure Notes:

1. The DONE pin is by default an open-drain output. An external pull-up resistor is required.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. CCLK signal integrity is critical.
4. A series resistor should be considered for the data path from the flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.
5. The FPGA V_{CCO_0} supply must be compatible with the VCC for the I/O of the flash device.
6. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups, or it can be tied to V_{CCO_0} to 3-state the SelectIO pins after power-up and during configuration.
7. Bank 65 or Bank 66 is used for the multi-function configuration I/O.