FPGA master configuration modes are
self-loading and available with a serial or parallel data path. In master mode, the
FPGA PDI typically resides in nonvolatile memory on the same board. The FPGA
internally generates a configuration clock signal called CCLK, and the FPGA controls the configuration process by sending a
clock and chip select to the flash memory device. See the following figure for
details.
The CCLK internal frequency is selected with
a PDI option. For the master configuration modes an alternate clock, the external
master configuration clock (EMCCLK), can be enabled
(see External Master Configuration Clock). Master SPI mode supports a
serial x1 option as shown in Figure 1, but the mode also supports x2 and x4 data bus
widths.