MASTER_JTAG provides control of the JTAG port from the FPGA logic, overriding the external pins. When MASTER_JTAG is instantiated, the external JTAG port is disabled at the end of configuration startup (EOS). Therefore MASTER_JTAG should not be instantiated except for a design requiring internal access to the JTAG port. The MASTER_JTAG primitive is not used for eFUSE programming in Spartan UltraScale+ FPGAs. Instead, Spartan UltraScale+ FPGAs rely on the AXI32 primitive for eFUSE programming. Because the external JTAG port is disabled, MASTER_JTAG prevents the use of the Vivado device programmer and the Vivado logic analyzer.