The JTAG dedicated I/O supports boundary-scan operations, status register access, and boot operation. The JTAG interface provides base debug to assist with board or device bring-up issue isolation.
The TAP controller instructions are listed in TAP Controller and Architecture. The availability of an instruction depends on the state of the device as shown in the figure in this section. The device has a hardware-controlled JTAG security access gate that blocks the TAP/Boundary Scan until the device enters an authorized state (JTAG mode, firmware release, or secure unlock).
If JTAG is disabled, via the JTAG disable eFUSE, only the IDCODE and BYPASS JTAG instructions are available. This is a permanent setting and cannot be reverted.