JTAG Configuration - JTAG Configuration - UG860

For single-device configuration, the TAP controller commands are issued automatically if the part is being configured with AMD Vivado Design Suite. The download cable must be attached to the appropriate four JTAG pins (TMS, TCK, TDI and TDO) to deliver the programmable device image (PDI) from the computer port to the FPGA. See Vivado Design Suite User Guide: Programming and Debugging (UG908) for supported cables and PDI programming detail. The Vivado Design Suite hardware manager tool automatically checks that a valid AMD device is connected and drive the commands to deliver and/or verify that the configuration bits are properly managed.

The following figure shows a typical JTAG setup with the simple connections required to attach a single device to a JTAG signal header, which can be driven from an AMD programming cable under the control of the Vivado Design Suite or with a third-party JTAG test tool and STAPL file from Vivado HW Manager. The connections essential to configure the device in the JTAG configuration mode are shown.

Figure 1. JTAG Configuration Interface Example

Figure Notes:

1. The DONE pin is by default an open-drain output. An external pull-up resistor is required.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. See the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) for the VCCINT, VCCAUX, and VCCO_0 supply voltages.
4. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to VCCO_0 to 3-state the SelectIO pins after power-up and during configuration.

It is also possible to configure multiple devices in a chain, as shown in the following figure.

Figure 2. Boundary-Scan Chain of Devices