Introduction - Introduction - UG860

In serial configuration mode, the FPGA is configured by loading one configuration bit per CCLK cycle. CCLK is an input in slave serial mode. AMD Spartan™ UltraScale+™ FPGAs include two additional signals on this interface from other AMD UltraScale™ architecture-based FPGA families, the READY and CS_B. The READY signal must be monitored by the host and when the pin is asserted it indicates that the FPGA is ready to accept data. The chip select (CS_B) signal is an active-Low signal that must be asserted (CS_B=0) before sending data to the FPGA.