AMD Spartan™ UltraScale+™ FPGAs support IEEE standards 1149.1 and 1149.6 (ACJTAG), defining a test access port (TAP) and boundary-scan architecture. The TAP and boundary-scan architecture is commonly referred to collectively as JTAG. JTAG is an acronym for the Joint Test Action Group, the technical subcommittee responsible for developing the initial standard. The boundary-scan architecture is used to ensure the board-level integrity of individual components and the interconnections between them.
With multi-layer PC boards becoming increasingly dense and with more sophisticated surface mounting techniques in use, boundary-scan testing is becoming widely used as an important debugging tool.
Devices containing boundary-scan logic can send data out on I/O pins to test connections between devices at the board level. The circuitry can also be used to send signals internally to test the device-specific behavior. These tests are commonly used to detect opens and shorts at the board level.
In addition to connectivity testing, the boundary-scan architecture
offers flexibility for vendor-specific instructions, such as JCONFIG, which add the capability of loading configuration data
directly to FPGAs.
For compliance with the pre-configuration BSDL file description,
PUDC_B should be tied to VCCO_0 to disable pull-ups, which matches the pre-configuration BSDL file
disable result description of ‘Z’ for when a boundary-scan controller disables the
output to a pin. Otherwise, if PUDC_B is tied to
GND, pre-configuration weak pull-up resistors are enabled and the corresponding
output disable result of PULL1 in the BSDL file is
a more accurate match to the device pin behavior. However, to maximize boundary-scan
tests for external pull-up or pull-down resistors with pre-configured devices, the
default disable result value ‘Z’ in the pre-configuration BSDL file is recommended
for both settings of PUDC_B. All external pull-down
resistors must be sufficiently strong to override potential internal pull-ups that
are enabled when PUDC_B is tied to GND.
In addition, for compliance the PROGRAM_B pin must be High to have proper JTAG functionality. For
example, if the PROGRAM_B pin is held Low, the
IDCODE value might be incorrect.