Instruction Register - Instruction Register - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)
Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The instruction register (IR) is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel-loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the Instruction register from TDI.

The instruction register is 6 bits wide for Spartan UltraScale+ devices. See Spartan UltraScale+ Devices and JTAG IDCODEs. To invoke an operation an opcode is loaded into the Spartan UltraScale+ FPGAs JTAG boundary-scan Instruction register. The following table describes the boundary-scan instructions for Spartan UltraScale+ devices.

Table 1. JTAG Boundary-Scan Instructions
Boundary-Scan Command Binary Code [5:0] Description
EXTEST 100110 Enables 1149.1 boundary-scan EXTEST operation
EXTEST_PULSE 111100 Enables 1149.6 EXTEST_PULSE operation for transceivers
EXTEST_TRAIN 111101 Enables 1149.6 EXTEST_TRAIN operation for transceivers
SAMPLE/PRELOAD 000001 Enables 1149.1 boundary-scan SAMPLE/PRELOAD operation
USER1 000010 Access user-defined register 1
USER2 000011 Access user-defined register 2
USER3 100010 Access user-defined register 3
USER4 100011 Access user-defined register 4
USERCODE 001000 Enables shifting out user code
IDCODE 001001 Enables shifting out of IDCODE
HIGHZ_IO 001010 Disable user I/O pins only while enabling the Bypass register
BYPASS 111111 Enables 1149.1 BYPASS operation
JCONFIG 000101 Access the configuration bus for configuration
JRDBK 000100 Access the configuration bus for readback
JPROG 001011 Equivalent to PROGRAM_B pin and sets the internal mode pins to JTAG. This enables JTAG access when the M[2:0] are not physically set to the JTAG configuration mode
SYSMON_DRP 011100 System Monitor DRP access through JTAG. See the UltraScale Architecture System Monitor User Guide (UG580).
READ_DNA 110010 Read eFUSE DNA value
SYS_RST 110111 System reset instruction
STATUS 011111 Reads the JTAG_STATUS register
ERROR_STATUS 111110 Reads the PMC ERROR_STATUS register for error management
FW_STATUS 011101 Reads the PMC FW_STATUS register for PLM debug, when BITSTREAM.CONFIG.MULTIBOOT_DEBUG property is enabled
RESERVED All other codes AMD reserved instructions

The following table shows the instruction capture values loaded into the IR as part of an instruction scan sequence.

Table 2. Instruction Capture Value
  IR[5] IR[4] IR[3] IR[2] IR[1:0]  
TDI → 0 0 0 0 01 → TDO