Initial Debug Steps - Initial Debug Steps - UG860

During the configuration process there are basic checks that can be performed to debug and isolate any issues encountered. AMD Spartan UltraScale+ FPGAs PDI format includes a signature pattern (XLNX) that should be checked in the initial boot header. After the signature is seen, the BootROM will run software checks and initiate the configuration. The CCLK can be checked to ensure the default configuration rate is seen and then increased rate if an option is selected. Basic checks that can be performed include:

• Try configuration using a different mode. For example, if configuring from a flash device try changing the mode pins to JTAG configuration mode and downloading the PDI with the Vivado Design Suite.
• Try configuration with a different PDI image. If possible, have a known-good PDI image with a simple design that can be used as a test.
• If using a higher speed CCLK setting or external master configuration clock, try a slower clock frequency setting.
• Reduce the number of non-default configuration PDI options selected.
• Try applying additional clocks at the end of configuration if the device is in a Slave boot mode and not starting up.
• Verify that the data is being received properly at the destination devices.
• Verify that the latest version of the tools is used.