The INIT_B pin is active-Low and
indicates when the device is in the reset state and initializing the device. Spartan
UltraScale+ FPGAs
will drive the INIT_B pin low at power-up or
after reset on when properly powered (See
Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching
Characteristics (DS930) for power rail values and power sequencing). In UltraScale+ devices,
the INIT_B pin might be seen as High (because of
external resistors on board for INIT_B) for
approximately 40 ms after power ON. The initial High time depends on the POR_OVERRIDE setting. With POR_OVERRIDE Low, the High time is approximately 40 ms. With POR_OVERRIDE High, the High time is approximately 9
ms. After the device is initialized the INIT_B is
released to a high impedance state. If the FPGA detects an error then the INIT_B is driven low. The INIT_B status signal provides key debug information during
configuration.