The internal configuration logic can detect the intended I/O width of
the QSPI interface using the width detection parameter value
(0x665599AA). During the SPI configuration mode process, the
internal configuration logic firmware configures the controller with 4-bit I/O. Then
the SPI device is read in 1-bit mode. It reads the width detection parameter in the
PDI header. If the width detection parameter is equal to
0x665599AA, then it is assumed a valid header was found requesting
a 4-bit I/O configuration. After reading the width detection parameter in 1-bit
mode, the configuration firmware attempts to read the parameter in 4-bit mode. If
4-bit mode fails, it tries 2-bit mode bus width to attempt access to the QSPI
device. The Spartan UltraScale+ FPGA internal
configuration logic always attempts to use the widest width working on a setup. If a
valid header is not detected then the BootROM increments the MultiBoot register
address offset by 32 KB and attempts to locate the valid header. This is repeated
until the search limit.