FW_STATUS Register - FW_STATUS Register - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)

Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The FW_STATUS register is read-only data register that contains PMC PLM status information for debug when the BITSTREAM.CONFIG.MULTIBOOT_DEBUG option is enabled. See the following table for the ERROR_STATUS register bit fields.

Table 1. FW_STATUS Register Description
Name Bit Index
PMC_FW_NCR_FLAG 95
PMC_FW_CR_FLAG 94
PMC_FW_ERROR_DATA 93:64
PMC_FW_STATUS(1) 63:32
PMC_FW_DATA 31:0
  1. PMC_FW_STATUS field provides PLM status information. Example: PMC_FW_STATUS [63:32]=0x00000010 indicates a full PDI load was completed successfully, and PMC_FW_STATUS [63:32]=0x000000AU can indicate the user configured clocks (related to improved performance OSPI DDR enable, >50MHz configrate, or EMCCLK) reinitialization with the flash failed.