External Master Configuration Clock - External Master Configuration Clock - UG860

By default, the master configuration modes use an internally generated configuration clock source (CCLK) specified by a PDI generation option (BITSTREAM.CONFIG.CONFIGRATE). Using this clock option is convenient because an external clock generator source is not required. However, for applications where configuration time reduction is critical, the external master configuration clock (EMCCLK) should be used. The EMCCLK clock allows the use of a more precise external clock source than the Spartan UltraScale+ FPGA's internal clock with the master CCLK frequency tolerance (FMCCKTOL ). For example, CCLK has a maximum frequency of 125 MHz with a 15% tolerance in the master OSPI configuration mode. This limits the maximum CCLK frequency in that configuration mode to 102MHz due to the available BITSTREAM.CONFIG.CONFIGRATE setting options. An external master configuration clock (EMCCLK) source can enable frequencies up to the maximum specification. UltraScale+ FPGAs support the ability to dynamically switch to an external clock source (EMCCLK) when in a master mode.

Enable the external clock source option by:

1. Enabling the PDI generation option (BITSTREAM.CONFIG.EMCCLK) and selecting a frequency within the data sheet specification. The default is disable (use the internal CCLK).
2. Connecting the EMCCLK pin on the board to your board's oscillator or other clock source.

Use good signal integrity design practices, especially for very high-speed clocks, to avoid signal integrity issues that can cause errors during configuration. EMCCLK is a single-ended clock input.

The configuration begins with the CCLK generated by the FPGA internal oscillator until the PDI header is read. If the BITSTREAM.CONFIG.EMCCLK option is enabled then the FPGA switches from the CCLK to the clock found on the EMCCLK pin.