ERROR_STATUS Register - ERROR_STATUS Register - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)
Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The ERROR_STATUS register is read-only data register that contains error conditions associated with the PMC and configuration controller. See the following table for the ERROR_STATUS register bit fields.

Table 1. ERROR_STATUS Register Description
Name Bit Index (1)
PMC_BOOT_ERR_DATA 2 60:31
DFX_UNEXPECTED_ACTIV_ERR 30
JTAG_TOGGLE_ERR 29
EFUSE_CACHE_ERR 28
ROM_VALID_ERR 27
PMC_FW_NCR_ERR 26
PMC_FW_CR_ERR 25
PMC_BOOT_NCR_ERR 24
PMC_BOOT_CR_ERR 23
SBI_SMAP_OVF_ERR 22
SSS_CFG_ERR 21
EFUSE_RD_ERR 20
EFUSE_PGM_ERR 19
OSPI_ERR 18
SBI_JTAG_OVF_ERR 17
SBI_SS_OVF_ERR 16
SBI_MCAP_OVF_ERR 15
SBI_SMAP_CONFIG_ERR 14
SBI_AXI_SLVERR 13
SBI_SMAP_ABORT 12
RESERVED 11:8
CCU_TAMPER_FABRIC 7
SYSMON_OT 6
CCU_BAD_PR_FORMAT 5
CCU_SEU_ECC_ERR 4
CCU_SEU_CRC_ERR 3
CCU_CRC_ERR 2
CCU_IDCODE_ERR 1
CCU_SLVERR 0
  1. After INIT_B pin deassertion after POR, bit fields ERROR_STATUS [60:31] and [24:23] should be reviewed for any errors that occur during the BootROM phase. The remaining ERROR_STATUS register bit fields are valid indicators after the INIT_B pin is released and PLM initiated.
  2. Refer to Table 1 for more information.