Each FPGA has one set of 32 nonvolatile, user-defined, one-time-programmable eFUSE bits. These bits are commonly programmed by the user to define a custom user design ID.
These 32 bits define the values in the FUSE_USER configuration register. Depending on the read/write access bits in the CNTL register, the 32 bits can be read through the JTAG port, with bit 0 shifted out first.
For internal access, the EFUSE_USR primitive must be instantiated. EFUSE_USR provides parallel access to all 32 bits.
The EFUSE_USR primitive is identical to that in the 7 series and directly migrates.