Differences from Previous Generations - Differences from Previous Generations

The Spartan UltraScale+ FPGAs include a PMC dedicated configuration controller, advancement on security features, updates on configuration modes, and improvements on key configuration features. The numerous enhancements from the UltraScale architecture-based FPGAs warrant a unique configuration user guide specific to these devices.

This section highlights the configuration and security differences from past FPGA devices. The UltraScale+ FPGAs provide a higher performance internal configuration clock (CCLK) with up to double the max frequency with less frequency variation. The UltraScale architecture-based FPGAs also offer a dedicated pin (POR_OVERRIDE) that can be set to reduce the delay when you know the power supplies will ramp quickly for configuration time.

The media configuration access port (MCAP) provides a connection to the integrated block for PCI Express®. MCAP is provided in select FPGAs as shown in Figure 1. These can support authentication and encryption on MCAP. A small initial PDI can be loaded quickly at power-up to enable the PCIe interface. The rest of the configuration can be loaded through the PCIe interface. This is known as tandem PCIe and it is supported on all Spartan UltraScale+ FPGAs with the PCIE4CE. See the UltraScale Architecture and Product Data Sheet: Overview (DS890) for more information. The following tables summarize key differences between Spartan UltraScale+ FPGAs, 7 series FPGAs, and other UltraScale architecture-based FPGAs.

Table 1. Differences Between Families: General
Feature Description	Spartan UltraScale+ FPGAs	Artix UltraScale+, and Virtex UltraScale+ FPGAs	Kintex UltraScale and Virtex UltraScale FPGAs	7 Series FPGAs
Configuration Controller	PMC dedicated configuration controller (runs BootROM/PLM)	Configuration engine
Programming image	Programmable device image (PDI)	Bitstream (.bit)
Fallback	Yes, increments by 32 KB until reaches search llimit	Yes, jumps to address `0x00000000`
Readback CRC	No, use SEM IP instead		No, use SEM IP instead (SEM IP is not supported in KU025)	Yes
MCAP	Yes ⁽¹⁾	Yes		N/A
SelectMAP Readback (Capture and Verify)	No	Yes
Configuration frame size (32-bit words)	93		123	101
MCAP is supported by select family members. Refer to Figure 1.

The Spartan UltraScale+ architecture-based FPGAs support the internal configuration access port (ICAP) for soft error mitigation (SEM) IP. See the following tables for additional design entry primitive differences.

Table 2. Differences Between Families: Design Entry
Feature Description	Spartan UltraScale+ FPGAs	Artix UltraScale+, and Virtex UltraScale+ FPGAs	Kintex UltraScale and Virtex UltraScale FPGAs	7 Series FPGAs
AXI32 primitive⁽¹⁾	Yes, supports runtime access to crypto blocks AES-GCM, SHA3, PUF, point multiplier for ECC, TRNG, eFUSE programming, and post-configuration flash programming	No
FUSE_CLK primitive	Yes, used for eFUSE programming	No
SEMIP	Yes, faster, uses FRAME_ECCE4	Yes, faster, uses FRAME_ECCE4	Yes (except KU025), faster, uses FRAME_ECCE3	Yes, uses FRAME_ECCE2
Device DNA	DNA_PORTE2, 96 bits	DNA_PORTE2, 96 bits		DNA_PORT, 57 bits
MASTER_JTAG Primitive	Yes, internal secure access to the JTAG logic	Yes, internal secure access to the JTAG logic		N/A
CAPTUREE2 Primitive	No			Yes
FRAME_ECC Primitive	FRAME_ECCE4, reserved for SEM IP		FRAME_ECCE3, reserved for SEM IP	FRAME_ECCE2
ICAP Primitive	ICAPE3 reserved for SEM IP; 32-bit, additional status signals	ICAPE3; 32-bit, additional status signals		ICAPE2; 8-bit, 16-bit, 32-bit
STARTUP Primitive	STARTUPE3, adds access to dedicated configuration pins (`FCS_B` and `D[03:00]`), for post configuration access, KEYCLEARB used as secure use case tamper_fabric_b	STARTUPE3		STARTUPE2
The AXI32 primitive is accessed with the IP integrator (IPI) with the PMC Bridge IP or using the XPM_PMC_BRIDGE module to instantiate AXI32 in the user design.

Spartan UltraScale+ FPGAs support similar configuration interfaces as the other UltraScale architecture-based FPGAs and 7 series FPGAs. The following table summarizes the configuration mode differences.

Table 3. Configuration Modes Comparison
Configuration Mode	Spartan UltraScale+ FPGAs	Kintex and Virtex UltraScale FPGAs, Artix, and Virtex UltraScale+ FPGAs	7 series FPGAs
Slave Serial	Yes⁽¹⁾	Yes	Yes
Slave SelectMAP	Yes⁽¹⁾	Yes	Yes
JTAG	Yes⁽²⁾	Yes	Yes
Master SPI (x1, x2, x4)	Yes⁽³⁾	Yes	Yes
Master OSPI (x1, x8)	Yes⁽⁴⁾	No	No
Master SPI (dual quad, x8)	No	Yes	No
Master BPI	No	Yes	Yes
Master Serial	No	Not recommended⁽⁴⁾	Yes
Master SelectMAP	No	Not recommended⁽⁴⁾	Yes
Spartan UltraScale+ FPGAs require additional signals for the slave serial configuration mode (`CS_B` and `READY`) and slave SelectMAP configuration mode (`BUSY`). See the specific configuration mode chapter for additional details. Spartan UltraScale+ FPGAs JTAG mode supports secure boot and configuration. For JTAG boundary-scan test, the configuration mode pins must be set to JTAG configuration mode (M[2:0]=101) and the PCB design must allow for the M[2:0] pins to be changed between the JTAG mode for JTAG boundary-scan test and the primary configuration mode for configuration. See Configuration and Mode Setting for more information. Master SPI configuration mode has two `M[2:0]` selections in Spartan UltraScale+ FPGAs, SPI_24 for 24-bit addressing or SPI_32 for 32-bit addressing flash access. Master SPI and master OSPI configuration modes are recommended over the legacy master serial and master SelectMAP configuration modes because they provide a wider flash density selection and lower cost solution.

The master configuration modes are optimized to work with third-party flash memories. The master SPI configuration mode interface connects to standard SPI NOR flash memory devices. The master OSPI configuration mode interface connects to select octal SPI flash memory devices. See Vivado Design Suite User Guide: Programming and Debugging (UG908) for supported flash with each FPGA.

Tip: The Spartan UltraScale+ FPGAs add a new configuration mode to configure from select Octal SPI flash memory. The resulting 8-bit wide configuration data bus reduces the configuration time while still allowing for the use of standard, high-speed, low-cost SPI NOR configuration memories.

Additional configuration mode feature changes are summarized in the following table.

Table 4. Differences Between Families: Configuration Mode Features
Feature Description	Spartan UltraScale+ FPGAs	Artix UltraScale+, and Virtex UltraScale+ FPGAs
Master SPI or Slave SelectMAP Daisy-chain	No	Yes
Master SPI auto bus detection	Yes	No
JTAG Access in Non-JTAG mode pin setting	JTAG PDI load available after issue of JPROG JTAG instruction	JTAG bitstream load available

There are new configuration pins associated with select modes. The following table highlights key variations from past generations.

Table 5. Differences Between Families: Configuration Pin
Feature Description	Spartan UltraScale+ FPGAs	Artix UltraScale+, and Virtex UltraScale+ FPGAs	Kintex UltraScale and Virtex UltraScale FPGAs	7 Series FPGAs
POR_OVERRIDE	Yes			No
Configuration Bank Voltage Selector (CFGBVS) pin	No		Yes
RDWR_B and FCS_B Pins	RDWR_FCS_B combined, dedicated, reduced number of configuration pins			RDWR_B FCS_B; separate, multi-function
D[03:00], PUDC_B	Dedicated, included in STARTUPE3			Multi-function, not included in STARTUPE2
Slave SelectMAP BUSY multi-function pin	Yes	No
Slave Serial CS_B and READY dedicated pins	Yes	No
Slave Serial DOUT pin	Dedicated, for slave serial daisy-chain	Multi-function, for slave serial, master serial, or SPI x1 mode daisy-chain.
Master SPI configuration mode settings	M[2:0]=001 for SPI_24 (24 bit addressing); M[2:0]=010 for SPI_32 (32 bit addressing)	M[2:0]=001
CCLK (configuration rate options)	21, 25, 31, 42, 51, 56, 63, 72, 85, 102, 127	2.7, 5.3, 8.0,10.6, 21.3, 31.9,36.4, 51.0, 56.7,63.8, 72.9, 85.0,102.0, 127.5,170.0	3, 6, 9, 12, 22,33, 40, 50, 57,69, 82, 87, 90,110, 115, 130, 148	3, 6, 9, 12, 16,22, 26, 33, 40,50, 66

In addition to the dedicated configuration bank 0, Spartan UltraScale+ FPGAs have one or two multi-function I/O banks that contain additional configuration mode pins. The multi-function I/O banks (Bank 65, Bank 66) availability depend on the family device member. See the UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) for more details. Table 1 describes the configuration pin usage and the associated banks. Configuration interfaces can be powered at 1.5V or 1.8V. These devices also support the multi-function I/O configuration banks at 1.2V to 3.3V when the bank is not used by the configuration mode interface.

Table 6. Differences Between Families: Power Rail and Banks
Feature Description	Spartan UltraScale+ FPGAs	Artix UltraScale+, and Virtex UltraScale+ FPGAs	Kintex UltraScale and Virtex UltraScale FPGAs	7 Series FPGAs
Bank 0 Voltage	1.5V-1.8V	1.5V-1.8V	1.5V-3.3V
Multi-function banks voltage for configuration⁽¹⁾	1.5V-1.8V	1.5V-1.8V	Kintex except KU095: 1.5V-3.3V; Virtex and KU095: 1.5V-1.8V	1.5V-3.3V
Multi-function banks⁽¹⁾	65, 66	65		14, 15
Battery-Backed RAM (BBRAM) and VBATT power rail	No	Yes
Multi-function configuration banks can run at 1.2V to 3.3V for user design logic if the bank is not used by the selected configuration mode. Multi-function I/O bank usage is dependent on the device and configuration mode. See Configuration Pins for more information.

Security feature advancements from past families are summarized in the following table.

Table 7. Differences Between Families: Security
Feature Description	Spartan UltraScale+ FPGAs	Artix UltraScale+, and Virtex UltraScale+ FPGAs	Kintex UltraScale and Virtex UltraScale FPGAs	7 Series FPGAs
Encryption	AES-GCM; similar performance to standard configuration	AES-GCM; similar performance to standard configuration		AES-CBC
Authentication	AES-GCM, HSS, ECDSA P-384, LMS⁽¹⁾	AES-GCM and RSA	AES-GCM and RSA (except KU025)	HMAC
PUF	Yes	No
TRNG	Yes	No
A-HWRoT/S-HWRoT Secure Boot	Yes	No
Access to crypto blocks (AES-GCM, SHA3, PUF, point multiplier for ECC, TRNG)	Yes	No
See Table 1 for details on which devices are supported.

See Table 1 for additional information on boot and configuration trade-offs for early planning phases of a design.

Differences from Previous Generations - Differences from Previous Generations - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)