The Spartan UltraScale+ FPGAs high-level design flow in the Vivado Design Suite is similar to other UltraScale+ FPGAs. The key difference is the programming file generation step. Other UltraScale+ FPGAs use the bitstream programming file. Spartan UltraScale+ FPGAs require additional information for the PMC configuration controller to successfully boot and configure. The additional information is included in the file programming format called a programmable device image (PDI). See Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information.
Important:
Spartan
UltraScale+ FPGAs
require a programmable device image (.pdi) and cannot be programmed with a
bitstream (.bit) file.
Figure 1. Spartan UltraScale+ FPGA System Level Design Flow
Figure Notes:
- For Spartan
UltraScale+
devices, the Vivado project mode (Flow Navigator
- Program and Debug: Generate Device Image) will directly generate a PDI file
for programming. When using the Vivado
non-project mode, the write_bitstream command will generate the programmable
logic .rdco (bitstream data) and the design.bif that are inputs into Bootgen.
The Bootgen command must be run after generating the programmable logic .rdco.
See example command:
bootgen -arch spartanup -image <design.bif> -o <design.pdi>