Configuration Pins - Configuration Pins

Configuration Pins - Configuration Pins - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)

Document_ID

UG860

Release_Date

2026-07-27

Revision

v1.3 English

Each configuration mode has a corresponding set of interface pins that span up to three banks on the FPGA. HP I/O Bank 0 contains the dedicated configuration pins, used by every configuration interface. Multi-function configuration banks (Bank 65, Bank66) include select configuration interface pins. If the persist option is used, the multi-function I/O for the selected configuration mode remain active after configuration. The following tables show the configuration pins and their locations across the I/O banks. See Differences from Previous Generations for more information.

Table 1. Master Modes Configuration Pins
Pin Name	Bank⁽⁶⁾	Master SPI_24 or SPI_32			Master OSPI
Pin Name	Bank⁽⁶⁾	x1	x2	x4	x1	x8
POR_OVERRIDE	N/A	POR_ OVERRIDE	POR_ OVERRIDE	POR_ OVERRIDE	POR_ OVERRIDE	POR_ OVERRIDE
M[2:0]	0	SPI_24: M[2:0]=001 SPI_32: M[2:0]=010	SPI_24: M[2:0]=001 SPI_32: M[2:0]=010	SPI_24: M[2:0]=001 SPI_32: M[2:0]=010	M[2:0]=011	M[2:0]=011
TCK	0	TCK	TCK	TCK	TCK	TCK
TMS	0	TMS	TMS	TMS	TMS	TMS
TDI	0	TDI	TDI	TDI	TDI	TDI
TDO	0	TDO	TDO	TDO	TDO	TDO
PROGRAM_B	0	PROGRAM_B	PROGRAM_B	PROGRAM_B	PROGRAM_B	PROGRAM_B
INIT_B	0	INIT_B	INIT_B	INIT_B	INIT_B	INIT_B
DONE	0	DONE	DONE	DONE	DONE	DONE
CCLK	0	CCLK	CCLK	CCLK	CCLK	CCLK
PUDC_B ⁽¹⁾	0	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾
RDWR_FCS_B	0	FCS_B	FCS_B	FCS_B	FCS_B	FCS_B
D00_MOSI_DOUT	0	MOSI	D00_MOSI	D00_MOSI	-	-
D01_DIN	0	DIN	D01_DIN	D01_DIN	-	-
D02	0	-	-	D02	-	-
D03	0	-	-	D03	-	-
D[07:04]_OSPID[03:00]	65 or 66	-	-	-	OSPID[01:00]	OSPID[03:00]
D[11:08]_OSPID[07:04]	65 or 66	-	-	-	-	OSPID[07:04]
OSPI_ECC_FAIL	65 or 66	-	-	-	OSPI_ECC_FAIL	OSPI_ECC_FAIL
OSPI_RST_B	65 or 66	-	-	-	OSPI_RST_B	OSPI_RST_B
OSPI_DS	65 or 66	-	-	-	-	OSPI_DS
EMCCLK⁽²⁾	65 or 66	EMCCLK⁽²⁾	EMCCLK⁽²⁾	EMCCLK⁽²⁾	EMCCLK⁽²⁾	EMCCLK⁽²⁾
FCS1_B⁽³⁾	65 or 66	-	-	-	-	-
`PUDC_B` has special functionality during configuration but is independent of all configuration interfaces. See Table 1 for details. `EMCCLK` is used when the external master `CCLK` enable option enables `EMCCLK` as an input for clocking the master configuration modes. `FCS1_B` is only supported during post-configuration access of a dual-stacked SPI x4 flash. JTAG pins (`TCK`, `TMS`, `TDI`, `TDO`) are listed with all configuration modes as the JTAG interface is recommended to be included for debug. Dashes indicate that the pin is not used in the configuration mode and is high impedance and ignored during configuration. Bank 65 is used by devices: SU65P, SU100P, SU150P, and SU200P. Bank 66 is used by devices: SU10P, SU25P, SU35P, SU45P, and SU60P.

Table 2. Slave Modes Configuration Pins
Pin Name	Bank ⁽⁵⁾	JTAG	Slave Serial	Slave SelectMAP
Pin Name	Bank ⁽⁵⁾	x1	x1	x8	x16	x32
POR_OVERRIDE	N/A	POR_ OVERRIDE	POR_ OVERRIDE	POR_ OVERRIDE	POR_ OVERRIDE	POR_ OVERRIDE
M[2:0]	0	M[2:0]=101	M[2:0]=111	M[2:0]=110	M[2:0]=110	M[2:0]=110
TCK	0	TCK	TCK	TCK	TCK	TCK
TMS	0	TMS	TMS	TMS	TMS	TMS
TDI	0	TDI	TDI	TDI	TDI	TDI
TDO	0	TDO	TDO	TDO	TDO	TDO
PROGRAM_B	0	PROGRAM_B	PROGRAM_B	PROGRAM_B	PROGRAM_B	PROGRAM_B
INIT_B	0	INIT_B	INIT_B	INIT_B	INIT_B	INIT_B
DONE	0	DONE	DONE	DONE	DONE	DONE
CCLK	0	-	CCLK	CCLK	CCLK	CCLK
PUDC_B⁽¹⁾	0	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾	PUDC_B⁽¹⁾
RDWR_FCS_B	0	-	-	RDWR_B	RDWR_B	RDWR_B
D00_MOSI_DOUT⁽²⁾	0	-	DOUT⁽²⁾	D00	D00	D00
D01_DIN	0	-	DIN	D01	D01	D01
D02_CS_B	0	-	CS_B	D02	D02	D02
D03_READY	0	-	READY	D03	D03	D03
D[07:04]_OSPID[03:00]	65 or 66	-	-	D[07:04]	D[07:04]	D[07:04]
D[11:08]_OSPID[07:04]	65 or 66	-	-	-	D[11:08]	D[11:08]
D[31:12]	65	-	-	-	D[15:12]	D[31:12]
CSI_ B	65 or 66	-	-	CSI_B	CSI_B	CSI_B
BUSY	65 or 66	-	-	BUSY	BUSY	BUSY
`PUDC_B` has special functionality during configuration but is independent of all configuration interfaces. See Table 1 for details. `DOUT` is only used in a slave serial configuration daisy-chain for outputting data to the downstream. Otherwise, `DOUT` is high impedance. JTAG pins (`TCK`, `TMS`, `TDI`, `TDO`) are listed with all configuration modes as the JTAG interface is recommended to be included for debug. Dashes indicate that the pin is not used in the configuration mode and is high-impedance and ignored during configuration. Bank 65 is used by devices: SU65P, SU100P, SU150P, and SU200P. Bank 66 is used by devices: SU10P, SU25P, SU35P, SU45P, and SU60P.