Configuration Pin Definitions - Configuration Pin Definitions - UG860

Reduces T_POR time (from power up to INIT_B rise) as specified in Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930). Connect directly to V_CCINT for a shorter T_POR time if required and if supported by the power-up timing of the configuration data source. Connect to GND for standard longer POR delay.

Active-Low reset to configuration logic. When PROGRAM_B is pulsed Low, the FPGA configuration is cleared and a new configuration sequence is initiated. Configuration reset is initiated upon the falling edge, and configuration (that is, programming) sequence begins upon the following rising edge. PROGRAM_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process. If PROGRAM_B is held Low, JTAG operations can be restricted. Dedicated pins remain disabled while PROGRAM_B is held Low.

Connect PROGRAM_B to an external ≤ 4.7 kΩ pull-up resistor to V_{CCO_0} to ensure a stable High input. Recommended push-button to GND to enable manual configuration reset.

Active-Low FPGA initialization pin or configuration error signal. The FPGA drives this pin Low when the FPGA is in a configuration reset state, when the FPGA is initializing (clearing) its configuration memory, or when the FPGA has detected a configuration error. Note that INIT_B does not drive Low when V_CCINT is powered down. In UltraScale+ devices the INIT_B pin might be seen as High (because of external resistors on board for INIT_B) for approximately 40 ms after power ON. The initial High time depends on the POR_OVERRIDE setting. With POR_OVERRIDE Low, the High time is approx. 40 ms. With POR_OVERRIDE High, the High time is approx. 9 ms.)

Upon completing the FPGA initialization process, INIT_B is released to high-impedance at which time an external resistor is expected to pull INIT_B High. INIT_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process. When the BootROM detects a High at the INIT_B input after the initialization process, the FPGA proceeds with the remainder of the configuration sequence dictated by the M[2:0] pin settings. After configuration, INIT_B can optionally be leveraged to indicate when the FPGA has detected a configuration error.

Connect INIT_B to a 4.7 kΩ pull-up resistor to V_{CCO_0} to ensure clean Low-to-High transitions.

A High signal on the DONE pin indicates completion of the configuration sequence. The DONE output is open-drain.

In UltraScale+ devices the DONE pin might be seen as High (because of external resistors on board for DONE) for approximately 40 ms after power ON. (The initial High time depends on the POR_OVERRIDE setting. With POR_OVERRIDE Low, the High time is approx. 40 ms. With POR_OVERRIDE High, the High time is approx. 9 ms.)

Read/Write input controls whether the data pins are inputs or outputs. When RDWR_B is Low, an external device drives the SelectMAP data bus. Write operation solution support is available configuration. When RDWR_B is High, the Versal device drives the SelectMAP data bus, regardless of the CSI_B level. Read operation (SelectMAP readback) solution support is not available.

Data output for a serial configuration daisy-chain. If the device is in a serial configuration daisy-chain, then connect to the DIN of the downstream slave-serial FPGA.

Multi-function

Data Bus bits 11 to 4. A subset or all of the D[31:00] pins are the databus interface for SelectMAP modes. By default, data from the data bus is captured on the rising edge of CCLK. The remaining data pins are unused, ignored, and high impedance during configuration, and D[31:04] can be used as I/O after configuration.