Spartan UltraScale+ FPGAs are programmed from a programmable device image (.pdi) to boot and configure. Configuration features are enabled through PDI properties (BITSTREAM.<category>.<property>) that are set in a Xilinx design constraints (XDC) file or through a Vivado Tcl command before execution of the write_bitstream command. Some examples of configuration and security features that are enabled with a PDI property include increasing the CCLK rate, using the external master configuration clock pin, and enabling OSPI DDR mode. For details on the available PDI properties see the Vivado Design Suite User Guide: Programming and Debugging (UG908).