AMD Spartan™
UltraScale+™
FPGAs
have five configuration interfaces. The configuration interface is selected with the
configuration mode pins M[2:0].
The mode input pins M0, M1, and M2 pins must
be set at a constant DC voltage level, either through a pull-up or pull-down
resistor (<1 kΩ), or tied directly to ground or VCCO_0. For configuration
initiated via assertion of the PROGRAM_B pin, the
M[2:0] input values must be set before the
deassertion of PROGRAM_B. The M[2:0] input value must be held at least throughout
device configuration initialization, which is the period when the device is driving
INIT_B Low.
For detailed configuration interface timing information, see the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930). Each configuration interface corresponds to one or more configuration modes and bus widths, shown in the following table.
| Configuration Mode | M[2:0] | Bus Width | Clock Direction |
|---|---|---|---|
| JTAG(1) |
101
|
x1 | Input (TCK) |
| Master SPI_24(2) |
001
|
x1, x2, x4 | Output (CCLK) |
| Master SPI_32(2) |
010
|
x1, x2, x4 | Output (CCLK) |
| Master OSPI |
011
|
x1, x8 | Output (CCLK) |
| Slave SelectMAP |
110
|
x8, x16, x32 | Input (CCLK) |
| Slave Serial |
111
|
x1 | Input (CCLK) |
|
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