Spartan UltraScale+ FPGAs include all registers required by IEEE Std 1149.1. In addition to the standard registers, the family contains optional registers for simplified testing and verification (see the following table).
| Register Name | Register Length | Description |
|---|---|---|
| Boundary | Up to 3 bits per I/O | Controls and observes input, output, and output enable. |
| Instruction | 6 bit | Holds the current instruction opcode. |
| Bypass | 1 bit | Bypasses the device. |
|
Device Identification (IDCODE) |
32 bit | Captures the device IDCODE. |
| JTAG Configuration | N/A | Allows access to the configuration bus when using the JCONFIG instruction to load a programmable device image (PDI) and enables read-only connection from the internal configuration bus to the TDO pin. |
| USERCODE | 32 bit | Captures the user-programmable code. |
| User-Defined (USER1, USER2, USER3, and USER4) | Design specific | Design specific registers. |
| JTAG_STATUS | 48 bit | Captures the overall device status. |
| ERROR_STATUS | 61 bit | Captures the error status of the device. |
| FW_STATUS | 96 bit | Captures the PMC PLM status for when debug option enable |
| DNA | 96 bit | Captures the device DNA. |