At power-on the Spartan UltraScale+ FPGA internal FOSC_CORE_CLK runs, and for all configuration modes, the BootROM initializes the following control clocks:
- Internal PMC control clock frequency (FPMC_IRO_CLK) is set to 255 MHz.
- Internal configuration control unit (CCU) clock frequency (FCCU_IRO_CLK) is set to 127 MHz.
For Master SPI (SPI_24, SPI_32) or OSPI configuration modes, the configuration clock (CCLK) is set to 21 MHz.
Note: The PLM does not modify the BootROM
initialized PMC or CCU clock settings during configuration. The PLM only
modifies the CCLK if the user design has selected a change with the Spartan
UltraScale+ PDI
properties. See
Vivado Design Suite User Guide:
Programming and Debugging (UG908) for
the PDI properties.