The Spartan UltraScale+ FPGAs have on-chip Advanced Encryption Standard (AES) decryption and authentication logic that provides a high degree of design security. Without knowledge of the encryption key, adversaries cannot analyze an externally intercepted PDI to modify or clone the design. Encrypted FPGA designs cannot be copied or reverse-engineered without knowing the AES key.
The FPGA encryption system uses the AES-GCM (Advanced Encryption Standard - Galois/Counter Mode) authenticated encryption algorithm. The AES-GCM standard is an official standard supported by the National Institute of Standards and Technology (NIST) and the U.S. Department of Commerce (https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38d.pdf). An advantage of the AES-GCM algorithm is that it also supports built-in authentication. Although the AES-GCM algorithm is a self authenticating algorithm, it does so with a symmetric key, meaning that the key used to encrypt is the same as the one to decrypt. This key must be protected as it is secret.
The Spartan UltraScale+ FPGA AES system consists of software-based PDI file encryption and on-chip PDI decryption using a dedicated hardened AES engine with dedicated memory for storing the encryption key. UltraScale architecture-based FPGAs store the encryption key internally in the nonvolatile, one-time-programmable eFUSE. The encryption key can only be programmed onto the device through the external JTAG port or through the internal AXI32 primitive and cannot be read back. The encryption key can either be stored unencrypted or encrypted with the physically unclonable function (PUF). Spartan UltraScale+ FPGAs provide the option for black (encrypted) key storage of the AES key using a key encryption key (KEK) created using the PUF. In this case the AES key is stored in a secure encrypted form to protect the AES key.