The AXI32 primitive is the hardened 32-bit AXI4 interface from the programmable logic (PL) to the platform management controller (PMC). This primitive provides the PL with access to the PMC registers listed in Kintex UltraScale+ Gen 2 and Spartan UltraScale+ FPGA Register Reference (UG1679). The user PL design with this primitive can access key registers including the IDCODE, USERCODE, DNA _0, DNA_1, DNA_2, and the MULTI_BOOT. The primitive also supports run-time access to crypto blocks AES-GCM, SHA3, PUF, point multiplier for elliptic curve cryptography (ECC), true random number generator (TRNG), post-configuration flash programming, and eFUSE programming. Refer to the Spartan UltraScale+ Register Reference with Security Registers (UG1680) and the Spartan UltraScale+ SU45P-SU200P Register Reference Security Registers (UG1687) for additional details.
The AXI32 primitive is accessed with the IP integrator (IPI) with the PMC Bridge IP or using the XPM_PMC_BRIDGE module to instantiate AXI32 in the user design. For the AXI32, the AXI4 interface supports burst length 16, address signal limited to 28-bits, and AXI ID signals limited to 8-bits (256 possible IDs).