New design for dataflow
Syntax
create_dataflow_design [‑name <arg>] [‑min_bus_width <arg>] [‑quiet]
[‑verbose]Usage
| Name | Description |
|---|---|
[-name]
|
Design name |
[-min_bus_width]
|
Minimum width of Data buses in Dataflow Design Default: 16 |
[-quiet]
|
Ignore command errors |
[-verbose]
|
Suspend message limits during command execution |
Description
The create_dataflow_design command creates a dataflow design from a design that is loaded in memory. The command opens design after synthesis in viewer mode, it is not possible to edit the design, run flow commands, or most reporting commands on a dataflow design. Understanding dataflow gives a wider understanding of the design, leading to user actions that results in improved placement through floorplanning addressing congestion or timing closure issues.
A dataflow design has a trimmed down netlist based off the parent design. It is optimized to quickly trace wide datapaths through to important blocks that have an impact on place and route.
The dataflow netlist trims out:
- Single bit signals
- Buses that are below than the
min_bus_width - All flops
- Most LUTs
- Carry Look-Ahead elements
The dataflow netlist keeps:
- Buses that are greater than the
min_bus_width - Advanced primitives for example, tranceivers, processors, PCIe.
- LUTRAMs, BlockRAMs and URAMs
- AI Engine and DSP blocks
The dataflow netlist is a subset of the parent design netlist. All the cell objects in the dataflow design can be cross probed to the parent design but as it is a subset of the design, the opposite is not true. However, if the cell exists it can be cross probed.
When analyzing a dataflow design, there are three main entry points to analysis:
- Use the
get_dataflow_pathscommand - Use the Dataflow Hierarchy Browser to identify key large modules based on primitive usage
- Select objects either in the Netlist window or Schematic and expand by double clicking on pins or cells
Frequently there are reasons to examine the full netlist. For example, to see registers or reports such as a timing or congestion report. This is achieved through cross probing to other views. Cross probing happens when an object is selected and then the design is updated using the current_design command.
Arguments
-name: <arg> - The name of the design to be created, uses default name if no name is specified. The default name is based on the parent design name and min_bus_width. For example, impl_1 and 16, default name is dfvnl_16_impl_1. Itis recommended to include dfv in the name so that it is distinct from a parent design.
-min_bus_width: (Optional) Changes the minimum bus width for buses is required in the design. Increasing the width likely results in a smaller netlist.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
set_msg_config command.Examples
To cross probe between different designs on a selected object, identify the available designs. In the following example,impl_1 is the opened implemented design and dfvnl is an open dataflow design.
get_designs
>> impl_1 dfvnl_16_impl_1The following example switches design to impl_1.
current_design impl_1The following example switches back to the dataflow design.
current_design dfvnl_16_impl_1