create_dataflow_design - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

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2024.1 English

New design for dataflow


create_dataflow_design [‑name <arg>] [‑min_bus_width <arg>] [‑quiet]


Name Description
[-name] Design name
[-min_bus_width] Minimum width of Data buses in Dataflow Design Default: 16
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution


Netlist, Project


The create_dataflow_design command creates a dataflow design from a design that is loaded in memory. The command opens design after synthesis in viewer mode, it is not possible to edit the design, run flow commands, or most reporting commands on a dataflow design. Understanding dataflow gives a wider understanding of the design, leading to user actions that results in improved placement through floorplanning addressing congestion or timing closure issues.

A dataflow design has a trimmed down netlist based off the parent design. It is optimized to quickly trace wide datapaths through to important blocks that have an impact on place and route.

The dataflow netlist trims out:

  • Single bit signals
  • Buses that are below than the min_bus_width
  • All flops
  • Most LUTs
  • Carry Look-Ahead elements

The dataflow netlist keeps:

  • Buses that are greater than the min_bus_width
  • Advanced primitives for example, tranceivers, processors, PCIe.
  • LUTRAMs, BlockRAMs and URAMs
  • AI Engine and DSP blocks

The dataflow netlist is a subset of the full design netlist. All the cell objects in the dataflow design can be cross probed to the full design but as it is a subset of the design, the opposite is not true. However, if the cell exists it can be cross probed.

When analyzing a dataflow design, there are three main entry points to analysis:

  1. Use the get_dataflow_paths command
  2. Use the Dataflow Hierarchy Browser to identify key large modules based on primitive usage
  3. Selecting objects either in the Netlist window or Schematic and expanding by double clicking on pins or cells

Frequently there are reasons to examine the full netlist. For example, to see registers or reports such as a timing or congestion report. This is achieved through cross probing to other views. Cross probing happens when an object is selected and then the design is updated using the current_design command.


-min_bus_width: (Optional) Changes the minimum bus width for buses to be kept in the design. Increasing will likely result in a smaller netlist.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.


To cross probe between different designs on a selected object, identify the available designs. In the following example,impl_1 is the opened implemented design and dfvnl is an open dataflow design.

>> impl_1 dfvnl

The following example switches design to impl_1.

current_design impl_1

The following example switches back to the dataflow design.

current_design dfvnl