create_bd_intf_port - 2025.2 English - UG835

Description

Create a new IP integrator subsystem design interface port. An IP integrator interface is a grouping of signals that share a common function, and can include both individual signals and buses that share a related function. An AXI4-Lite master, for example, is an interface that includes a large number of individual signals plus multiple buses.

To create a single connection port, or common bus port, use the create_bd_port command.

This command returns the name of the newly created interface port object if successful, and returns nothing if it failed.

Arguments

-vlnv <arg> - (Optional) The Vendor:Library:Name:Version (VLNV) attribute of the interface port object to be added to the subsystem design. The VLNV attribute identifies the object in the IP integrator catalog.

-mode <arg> - (Optional) Defines the mode of the interface pin. Accepted values are Master, Slave, System, MirroredMaster, MirroredSlave, MirroredSystem, Monitor.

-default_portmap - Creates default port-maps for this external bus-interface. Refer to bus-interface definition in the Vivado IP catalog for the ports instantiated in the default portmap.

AWID { physical_name axi_intf_0_awid direction O } AWPROT { physical_name axi_intf_0_awprot direction O left 2 right 0 } "

<name> - (Required) The name of the interface port to add to the subsystem design.

Example

The following example creates a new IP integrator interface port and adds it to the current subsystem design:

create_bd_intf_port -vlnv xilinx.com:interface:diff_clock_rtl:1.0 \
   -mode Slave diff_clock_rtl

The following example creates a GPIO_1 interface for bus interface VLNV xilinx.com:interface:gpio with default portmap. It includes TRI_I, TRI_O, TRI_T logical ports with GPIO_1_tri_i in direction input, GPIO_1_tri_o in direction output, and GPIO_1_tri_t in direction output respectively.

set GPIO_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 -default_portmap GPIO_1 ]

The following example creates a GPIO_0 interface for bus interface VLNV xilinx.com:interface:gpio with custom portmap as passed in the dictionary input. It includes TRI_I, TRI_O, TRI_T logical ports with GPIO_0_tri_i in direction input, GPIO_0_tri_o in direction output, and GPIO_0_tri_t in direction output respectively. The HDL_ATTRIBUTE.LOCKED property ensures that the custom portmap is maintained in the generated HDL on the GPIO_0 interface.

set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 -portmaps { \
                        TRI_I { physical_name GPIO_0_tri_i direction I } \
                         TRI_O { physical_name GPIO_0_tri_o direction O } \
                         TRI_T { physical_name GPIO_0_tri_t direction O } \
                         } \
                       GPIO_0 ]
set_property HDL_ATTRIBUTE.LOCKED {true} [get_bd_intf_ports GPIO_0]

The following example creates an axi_intf_0 interface for bus interface VLNV xilinx.com:interface:aximm_rtl:1.0 with custom portmap as passed in the dictionary input. The HDL_ATTRIBUTE.LOCKED property ensures that the custom portmap is maintained in the generated HDL for the axi_intf_0 interface.

set axi_intf_0  [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 -portmaps { \
ARADDR { physical_name axi_intf_0_araddr direction O } \
ARBURST { physical_name axi_intf_0_arburst direction O left 1 right 0 } \
ARCACHE { physical_name axi_intf_0_arcache direction O left 3 right 0 } \
ARID { physical_name axi_intf_0_arid direction O } \
ARLEN { physical_name axi_intf_0_arlen direction O } \
ARLOCK { physical_name axi_intf_0_arlock direction O } \
ARPROT { physical_name axi_intf_0_arprot direction O left 2 right 0 } \
ARQOS { physical_name axi_intf_0_arqos direction O left 3 right 0 } \
ARREADY { physical_name axi_intf_0_arready direction I left 0 right 0 } \
ARREGION { physical_name axi_intf_0_arregion direction O left 3 right 0 } \
ARSIZE { physical_name axi_intf_0_arsize direction O left 2 right 0 } \
ARUSER { physical_name axi_intf_0_aruser direction O } \
ARVALID { physical_name axi_intf_0_arvalid direction O left 0 right 0 } \
} \
axi_intf_0 ]
set_property HDL_ATTRIBUTE.LOCKED {true} [get_bd_intf_ports axi_intf_0]

See Also

• connect_bd_intf_net
• create_bd_intf_pin
• create_bd_port
• delete_bd_objs
• get_bd_intf_ports