create_bd_cell - 2025.2 English - UG835

Description

This command adds a cell from the AMD Vivado™ Design Suite catalog to the current subsystem design, creates a new hierarchical module to add to the subsystem design, or creates a new module by referencing the module definition from an HDL source file. Ensure to specify the following arguments based on the requirement:

• -vlnv: When adding an IP core from the catalog
• -type hier: When creating a new hierarchical block design module
• -type module and -reference: When creating a block design module that references an RTL module or entity declaration

  The module reference feature lets you add a module definition from an RTL file (Verilog or VHDL) into the block design. Add the source file containing the module definition to the project, or read into the design before creating a module reference. Refer to the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information on referencing modules.

This command returns the name of the newly created cell object or nothing if the command fails.

Arguments

-type [ IP | hier | container | module | inline_hdl ] - (Optional) Specifies the cell as the following:

• IP: IP from the Vivado IP catalog. This is the default type of block design cell created, but requires the use of the -vlnv option.
• hier: A new empty hierarchical block design module to add and populate in the current design.
• container: A block design container referenced from a BD file loaded in the source fileset. This requires the use of the -reference option.
• module: A hierarchical module referenced from a Verilog or VHDL file loaded in the source fileset. This requires the use of the -reference option.
• inline_hdl: A lightweight HDL block from the Vivado IP catalog inline_hdl library. This requires the use of the -vlnv option.

-reference <arg> - (Optional) Specifies the module name to reference from a loaded RTL design source file.

<name> - The name of the IP cell or hierarchical module to add to the current IP subsystem design.

Examples

The following example adds an AXI FIFO core from the IP integrator catalog to the current subsystem design, with the specified name:

create_bd_cell -vlnv xilinx.com:ip:axi_fifo_mm_s:4.0 axi_fifo_1

The following example creates a new block design container in the block design, referencing the specified module definition from a previously loaded BD source file:

set bdc [ create_bd_cell -type container -reference hier_0 bdc ]

The following example creates a new module in the block design, referencing the specified module definition from a previously loaded RTL source file:

create_bd_cell -type module -reference rtlRam rtlRam_0

The following example creates a new hierarchical module named myModule1 and moves the AXI FIFO from the prior example into the new module. myModule1 is set as the current instance in the subsystem design, creates a new module named myModule2, and adds to the current instance. Finally the current instance resets to point to the top-level of the subsystem design.

create_bd_cell -type hier myModule1
/myModule1
move_bd_cells /myModule1 [get_bd_cells /axi_fifo_1]
/myModule1
current_bd_instance /myModule1
/myModule1
create_bd_cell -type hier myModule2
/myModule1/myModule2
current_bd_instance
/

The following example adds an inline _hdl constant core from the inline _hdl library of IP integrator catalog to the current subsystem design with the specified name. Inline _hdl blocks are in-memory HDL blocks embedded in the subsystem design file. These blocks do not have any persistent storage on the disk.

create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilconstant:* ilconstant_0

See Also

• copy_bd_objs
• current_bd_instance
• move_bd_cells
• update_module_reference