config_flows - config_flows - 2026.1 English - UG835

Description

This command configures tool behavior and spans multiple stages of the Vivado core design flow from IP integrator to bitstream generation. The user selection affects synthesis, constraints, and HW debug. Use report_config_flows to report the current configuration.

Arguments

-mark_debug - (Optional) Allow optimization of nets with MARK_DEBUG instead of preserve. This includes both HDL attributes and XDC constraints. This setting makes it easier to move in and out of the design debug phases. The setting must be applied before opening and launching design runs or before opening design checkpoints. The following three values are supported:

• enable - Do not optimize MARK_DEBUG nets. This is default value.
• disable - Allow both synthesis and implementation to freely optimize MARK_DEBUG nets.
• synthesis_only - Synthesis does not optimize MARK_DEBUG nets so that they are available at the beginning of implementation, but MARK_DEBUG nets can be freely optimized during implementation.

-synth_strategy <arg> - (Optional) Sets the synthesis strategy for non-project flows. It can only specify one strategy. It supports the following values:

• Vivado Synthesis Defaults - Vivado Synthesis defaults.
• Flow_AreaOptimized_high - Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, applying lower thresholds for use of carry chain in comparators, and area optimized mux optimizations.
• Flow_AreaOptimized_medium - Performs general area optimizations including changing the threshold for control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of carry chain in comparators, and area optimized MUX optimizations.
• Flow_AreaMultThresholdDSP - Default option and the AreaMultThresholdDSP directive which lowers the threshold for inference of multipliers into DSP blocks.
• Flow_AlternateRoutability - Performs optimizations which creates alternative logic technology mapping, including disabling LUT combining, forcing F7/F8/F9 to logic, increasing the threshold of shift register inference.
• Flow_PerfOptimized_high - Turns OFF higher performance designs, resource sharing and sets the global fanout guide to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, and SRL are inferred with a larger threshold.
• Flow_PerfThresholdCarry - Default options and FewerCarryChains directive for less inference of carry chains, turns OFF the LUT combining, resource sharing off, retaining equivalent registers.
• Flow_RuntimeOptimized - Trades off Performance and Area for better runtime.

-impl_strategy <arg> - (Optional) Sets the implementation strategy for non-project flows. It specifies only one strategy.

• Vivado Advanced Implementation Defaults - Default settings for Advanced Implementation.
• Vivado Implementation Defaults - Default settings for Implementation (non Versal designs)
• Performance_Auto_1 - Best predicted directive for place_design (non Versal designs)
• Performance_Auto_2 - Second best predicted directive for place_design (non Versal designs)
• Performance_Auto_3 - Third best predicted directive for place_design (non Versal designs)
• Performance_Explore - Uses multiple algorithms for optimization, placement, and routing to get potentially better results.
• Performance_AggressiveExplore - Higher effort version of Explore algorithms.
• Performance_ExplorePostRoutePhysOpt - Similar to Performance_Explore, but enables the physical optimization step (phys_opt_design) with the explore directive after routing.
• Performance_ExploreWithRemap - Similar to Performance_ExplorePostRoutePhysOpt, but enables logic optimization step (opt_design) with the ExploreWithRemap directive.
• Performance_WLBlockPlacement - Minimize wirelength of connections to RAM and DSP blocks. For non‑Versal: Ignore timing constraints for placing Block RAM and DSPs, use wirelength instead.
• Performance_WLBlockPlacementFanoutOpt - Ignore timing constraints for placing Block RAM and DSPs, use wirelength instead, and perform aggressive replication of high fanout drivers (non Versal designs).
• Performance_EarlyBlockPlacement - Place RAM and DSP blocks in Global Placement. For non Versal designs: Finalize placement of Block RAM and DSPs in the early stages of global placement.
• Performance_NetDelay_high - To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. (high setting, most pessimistic)
• Performance_NetDelay_medium - To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. (medium setting, more pessimistic)
• Performance_NetDelay_low - To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections (low setting, least pessimistic) (non Versal designs).
• Performance_Retiming - Combines retiming in phys_opt_design with extra placement optimization and higher router delay cost.
• Performance_ExtraTimingOpt - Includes alternate algorithms for timing-driven optimization.
• Performance_RefinePlacement - Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router (non Versal designs).
• Performance_SpreadSLLs - A placement variation for SSI devices with tendency to move SLR crossings horizontally. (non‑Versal)
• Performance_BalanceSLLs - A placement variation for SSI devices with more aggressive crossings of SLR boundaries. (non‑Versal)
• Performance_BalanceSLRs - A placement variation for SSI devices to balance logic packing between SLRs.
• Performance_HighUtilSLRs - A placement variation for SSI devices with more logic packing in each SLR.
• Congestion_SpreadLogic_high - Spread logic throughout the device to avoid creating congested regions. (high setting: highest degree of spreading)
• Congestion_SpreadLogic_medium - Spread logic throughout the device to avoid creating congested regions. (medium setting)
• Congestion_SpreadLogic_low - Spread logic throughout the device to avoid creating congested regions. (low setting: lowest degree of spreading) (non‑Versal)
• Congestion_SSI_SpreadLogic_high - Spread logic throughout SSI device to avoid creating congested regions. (high setting: highest degree of spreading)
• Congestion_SSI_SpreadLogic_medium - Spread logic throughout SSI device to avoid creating congested regions. (medium setting: some spreading)
• Congestion_SSI_SpreadLogic_low - Spread logic throughout SSI device to avoid creating congested regions. (low setting: minimal spreading) (non Versal designs)
• Area_Explore - Uses multiple optimization algorithms to get potentially fewer LUTs.
• Area_ExploreSequential - Uses multiple optimization algorithms to get potentially fewer LUTs and registers.
• Area_ExploreWithRemap - Adds the remap optimization to reduce logic.
• Power_DefaultOpt - Adds power optimization (power_opt_design) to reduce power consumption (non Versal designs).
• Power_ExploreArea - Combines power optimization (power_opt_design) with sequential area reduction to reduce power consumption (non Versal designs).
• Flow_RunPhysOpt - Similar to the Implementation Run Defaults, but enables the physical optimization step (phys_opt_design) (non Versal designs).
• Flow_RunPostRoutePhysOpt - Similar to the Implementation Run Defaults, but enables the physical optimization step (phys_opt_design) before and after routing (non Versal designs).
• Flow_RuntimeOptimized - Each implementation step trades design performance for better runtime. Physical optimization (phys_opt_design) is disabled.
• Flow_Quick - Fastest possible runtime, all timing-driven behavior disabled. Useful for utilization estimation.

Examples

The following example sets the synthesis strategy to optimize for higher performance. After this, synth_design runs with the options configured by the Flow_PerfOptimized_high strategy:

config_flows -synth_strategy Flow_PerfOptimized_high

See Also

• config_implementation