Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586) - 4.2 English - Serves as a technical reference to using, customizing, and simulating DDR3 and DDR2 SDRAM, RLDRAM II, RLDRAM 3, QDRII+, and LPDDR2 memory interface cores. - UG586
Document ID
UG586
Release Date
2024-11-13
Version
4.2 English
DDR3 and DDR2 SDRAM Memory Interface Solution
Introduction
Features
Using MIG in the Vivado Design Suite
Customizing and Generating the Core
MIG Output Options
Pin Compatible FPGAs
Creating 7 Series FPGA DDR3 Memory Controller Block Design
Memory Selection
Controller Options
Create Custom Part
AXI Parameter Options
Setting DDR3 Memory Parameter Options
FPGA Options
Bank Selection
Summary
Memory Model License
PCB Information
Design Notes
Vivado Integrated Design Flow for MIG
Directory Structure and File Descriptions
Output Directory Structure
Directory and File Contents
<component name>/example_design/
example_design/rtl
example_design/rtl/traffic_gen
<component name>/example_design/par
<component name>/example_design/sim
<component name>/user_design
user_design/rtl/clocking
user_design/rtl/controller
user_design/rtl/ip_top
user_design/rtl/phy
user_design/rtl/ui
<component name>/user_design/xdc
Verify Pin Changes and Update Design
Quick Start Example Design
Overview
Implementing the Example Design
Simulating the Example Design (for Designs with the Standard User Interface)
Traffic Generator Operation
Modifying the Example Design
Modifying Port Address Space
Traffic Generator Signal Description
Memory Initialization and Traffic Test Flow
Simulating the Example Design (for Designs with the AXI4 Interface)
Setting Up for Simulation
Simulation Flow Using IES and VCS Script Files
Simulation Flow Using Vivado Simulator
Simulation Flow Using Questa Advanced Simulator
Simulation Flow Using VCS
Simulation Flow Using IES
Synplify Pro Black Box Testing
Core Architecture
Overview
User FPGA Logic
AXI4 Slave Interface Block
User Interface Block and User Interface
Memory Controller and Native Interface
PHY and the Physical Interface
IDELAYCTRL
User Interface
app_addr[ADDR_WIDTH – 1:0]
app_cmd[2:0]
app_en
app_hi_pri
app_wdf_data[APP_DATA_WIDTH – 1:0]
app_wdf_end
app_wdf_mask[APP_MASK_WIDTH – 1:0]
app_wdf_wren
app_rdy
app_rd_data[APP_DATA_WIDTH – 1:0]
app_rd_data_end
app_rd_data_valid
app_wdf_rdy
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
ui_clk_sync_rst
ui_clk
init_calib_complete
AXI4 Slave Interface Block
AXI4 Slave Interface Parameters
AXI4 Slave Interface Signals
Arbitration in AXI Shim
Time Division Multiplexing (TDM)
Round-Robin
Read Priority (RD_PRI_REG)
Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)
Write Priority (WRITE_PRIORITY, WRITE_PRIORITY_REG)
AXI4-Lite Slave Control/Status Register Interface Block
ECC Enable/Disable
Single Error and Double Error Reporting
AXI4-Lite Slave Control/Status Register Interface Parameters
AXI4-Lite Slave Control/Status Register Interface Signals
AXI4-Lite Slave Control/Status Register Map
AXI4-Lite Slave Control/Status Register Map Detailed Descriptions
User Interface Block
Native Interface
Command Request Signals
Write Command Signals
Read Command Signals
Native Interface Maintenance Command Signals
Clocking Architecture
Internal (FPGA) Logic Clock
Write Path (Output) I/O Logic Clock
Read Path (Input) I/O Logic Clock
IDELAY Reference Clock
Memory Controller
Bank Machines
Rank Machines
Column Machine
Arbitration Block
Reordering
Precharge Policy
Error Correcting Code
Read-Modify-Write
ECC Self-Test Functionality
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
I/O Architecture
PHY Control Block
Command Path
Datapath
Power-Saving Features
Calibration and Initialization Stages
Memory Initialization
PHASER_IN Phase Lock
PHASER_IN DQSFOUND Calibration
Write Leveling
Multi-Purpose Register Read Leveling
OCLKDELAYED Calibration
Write Calibration
Read Leveling
PRBS Read Leveling
Dynamic Calibration and Periodic Read Behavior
Temperature Monitor
Memory Controller to PHY Interface
Designing with the Core
Interfacing to the Core
AXI4 Slave Interface
AXI Addressing
Upsizing
User Interface
Command Path
Write Path
Read Path
User Refresh
User ZQ
Native Interface
User Refresh
User ZQ
Physical Layer Interface (Non-Memory Controller Design)
Customizing the Core
Design Guidelines
DDR3 SDRAM
Design Rules
Bank and Pin Selection Guides for DDR3 Designs
Pin Swapping
Bank Sharing Among Controllers
System Clock, PLL and MMCM Locations, and Constraints
DDR3 Component PCB Routing
VREF
VCCAUX_IO
Power System and Plane Discontinuities
Configuration
Termination
Trace Lengths
I/O Standards
DDR2 SDRAM
Design Rules
Pin Assignments
Bank and Pin Selection Guides for DDR2 Designs
Bank Sharing Among Controllers
Pin Swapping
Internal VREF
System Clock, PLL Location, and Constraints
Configuration
Termination
Trace Lengths
I/O Standards
Clocking
Input Clock Guidelines
Sharing sys_clk between Controllers
Information on Sharing BUFG Clock (phy_clk)
Information on Sync_Pulse
DDR3 Pinout Examples
Debugging DDR3/DDR2 Designs
Finding Help with AMD Adaptive Computing Solutions
Documentation
Solution Centers
Answer Records
Technical Support
Debug Tools
Example Design
Debug Signals
Vivado Design Suite Debug Feature
Reference Boards
Hardware Debug
General Checks
Calibration Stages
Determine the Failing Calibration Stage
Debug Signals
Debugging PHASER_IN PHASELOCKED Calibration Failures (dbg_pi_phaselock_err = 1)
Debugging PHASER_IN DQSFOUND Calibration Failures (dbg_pi_dqsfound_err = 1)
Debugging Write Leveling Failures (dbg_wrlvl_err = 1)
Debugging MPR Read Leveling Failures – DDR3 Only (dbg_rdlvl_err[1] = 1)
Debugging OCLKDELAYED Calibration Failures
Debugging Write Calibration Failures (dbg_wrcal_err = 1)
Debugging Read Leveling Failures (dbg_rdlvl_err[0] = 1)
Debugging PRBS Read Leveling Failures
Calibration Times
Debugging Data Errors
General Checks
Replicating the Error Using the Traffic Generator
Isolating the Data Error
Determining If a Data Error is Due to the Write or Read
Checking and Varying Read Timing
Automated Window Check
Manual Window Check
Analyzing Calibration Results
Interface Debug
AXI4-Lite Interfaces
AXI4-Stream Interfaces
CLOCK_DEDICATED_ROUTE Constraints
System Clock
Reference Clock
QDR II+ Memory Interface Solution
Introduction
Using MIG in the Vivado Design Suite
Customizing and Generating the Core
MIG Output Options
Pin Compatible FPGAs
Creating the 7 Series FPGA QDR II+ SRAM Design
Memory Selection
Controller Options
Create Custom Part
Memory Options
FPGA Options
Extended FPGA Options
I/O Planning Options
Bank Selection
System Pins Selection
Summary
PCB Information
Design Notes
Finish
Vivado Integrated Design Flow for MIG
Directory Structure and File Descriptions
Output Directory Structure
Verify Pin Changes and Update Design
Core Architecture
Overview
User Interface
Command Request Signals
Interfacing with the Core through the Client Interface
Clocking Architecture
Physical Interface
Interfacing with the Memory Device
PHY Architecture
Write Path
Output Architecture
Output Path
PHY Control Block
Pre-FIFO
Read Path
Data Capture
Calibration
Calibration of Read Clock and Data
Implementation Details
Data Alignment and Valid Generation
Write Calibration
Customizing the Core
Design Guidelines
Design Rules
Bank Sharing Among Controllers
Trace Length Requirements
Pinout Requirements
System Clock, PLL Location, and Constraints
Configuration
Termination
I/O Standards
Clocking
Input Clock Guidelines
Sharing sys_clk between Controllers
Information on Sharing BUFG Clock (phy_clk)
Information on Sync_Pulse
Debugging QDR II+ SRAM Designs
Introduction
Debug Tools
Example Design
Debug Signals
Vivado Design Suite Debug Feature
Simulation Debug
Verifying the Simulation Using the Example Design
Simulation Flow Using IES and VCS Script Files
Simulation Flow Using Vivado Simulator
Simulation Flow Using Questa Advanced Simulator
Simulation Flow Using VCS
Simulation Flow Using IES
Memory Initialization
Calibration
Test Bench
Proper Write and Read Commands
Synthesis and Implementation Debug
Verify Successful Synthesis and Implementation
Verify Modifications to the MIG Tool Output
Identifying and Analyzing Timing Failures
Hardware Debug
Clocking
Verify Board Pinout
Run Signal Integrity Simulation with IBIS Models
Run the Example Design
Debugging Common Hardware Issues
Isolating Bit Errors
Debugging the Core
Margin Check
Automated Margin Check
DEBUG_PORT Signals
Write Init Debug Signals
Read Stage 1 Calibration Debug Signals
Read Stage 2 Calibration Debug
CLOCK_DEDICATED_ROUTE Constraints
System Clock
Reference Clock
RLDRAM II and RLDRAM 3 Memory Interface Solutions
Introduction
Using MIG in the Vivado Design Suite
Customizing and Generating the Core
MIG Output Options
Pin Compatible FPGAs
Creating the 7 Series FPGAs RLDRAM II/RLDRAM 3 Memory Design
Memory Selection
Controller Options
Memory Options
FPGA Options
Extended FPGA Options
Bank Selection
System Pins Selection
Summary
PCB Information
Design Notes
Finish
Vivado Integrated Design Flow for MIG
Directory Structure and File Descriptions
Output Directory Structure
Verify Pin Changes and Update Design
Quick Start Example Design
Overview
Implementing the Example Design
Simulating the Example Design (for Designs with the Standard User Interface)
Traffic Generator Operation
Modifying the Example Design
Core Architecture
Overview
Client Interface
Command Request Signals
Interfacing with the Core through the Client Interface
Clocking Architecture
Physical Interface
Memory Controller
PHY Architecture
Write Path
Output Architecture
Read Path
Data Capture
Calibration
Calibration of Read Clock and Data
Implementation Details
Data Alignment and Valid Generation
Write Calibration
Customizing the Core
Design Guidelines
Design Rules
Bank Sharing Among Controllers
Trace Length Requirements
Pinout Requirements
RLDRAM II
RLDRAM 3
System Clock, PLL Location, and Constraints
Configuration
Termination
Manual Pinout Changes
I/O Standards
Clocking
Input Clock Guidelines
Sharing sys_clk between Controllers
Information on Sharing BUFG Clock (phy_clk)
Information on sync_pulse
Debugging RLDRAM II and RLDRAM 3 Designs
Introduction
Debug Tools
Example Design
Debug Signals
Vivado Design Suite Debug Feature
Simulation Debug
Verifying the Simulation Using the Example Design
Simulation Flow Using IES and VCS Script Files
Simulation Flow Using Vivado Simulator
Simulation Flow Using Questa Advanced Simulator
Simulation Flow Using VCS
Simulation Flow Using IES
Memory Initialization
Calibration
Test Bench
Proper Write and Read Commands
Synthesis and Implementation Debug
Verify Successful Synthesis and Implementation
Verify Modifications to the MIG Tool Output
Identifying and Analyzing Timing Failures
Hardware Debug
Clocking
Verify Board Pinout
Run Signal Integrity Simulation with IBIS Models
Run the Example Design
Debugging Common Hardware Issues
Isolating Bit Errors
Debugging the Core
DEBUG_PORT Signals
Write Init Debug Signals
Read Stage 1 Calibration Debug Signals
Read Stage 2 Calibration Debug
Write Calibration Debug Map
Margin Check
Automated Margin Check
Debugging Write Calibration
CLOCK_DEDICATED_ROUTE Constraints
System Clock
Reference Clock
LPDDR2 SDRAM Memory Interface Solution
Introduction
Features
Using MIG in the Vivado Design Suite
Customizing and Generating the Core
MIG Output Options
Pin Compatible FPGAs
Creating 7 Series FPGA LPDDR2 SDRAM Memory Controller Block Design
Memory Selection
Controller Options
Create Custom Part
Setting LPDDR2 SDRAM Memory Parameter Option
FPGA Options
Bank Selection
Summary
Memory Model License
PCB Information
Design Notes
Vivado Integrated Design Flow for MIG
Directory Structure and File Descriptions
Output Directory Structure
Verify Pin Changes and Update Design
Quick Start Example Design
Overview
Simulating the Example Design (for Designs with the Standard User Interface)
Traffic Generator Operation
Modifying the Example Design
Modifying Port Address Space
Traffic Generator Signal Descriptions
Memory Initialization and Traffic Test Flow
Memory Initialization
Traffic Test Flow
Setting Up for Simulation
Simulation Flow Using IES and VCS Script Files
Simulation Flow Using Vivado Simulator
Simulation Flow Using Questa Advanced Simulator
Simulation Flow Using VCS
Simulation Flow Using IES
Core Architecture
Overview
User FPGA Logic
User Interface Block and User Interface
Memory Controller and Native Interface
PHY and the Physical Interface
IDELAYCTRL
User Interface
app_addr[ADDR_WIDTH – 1:0]
app_cmd[2:0]
app_en
app_hi_pri
app_wdf_data[APP_DATA_WIDTH – 1:0]
app_wdf_end
app_wdf_mask[APP_MASK_WIDTH – 1:0]
app_wdf_wren
app_rdy
app_rd_data[APP_DATA_WIDTH – 1:0]
app_rd_data_end
app_rd_data_valid
app_wdf_rdy
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
ui_clk_sync_rst
ui_clk
init_calib_complete
User Interface Block
Native Interface
Command Request Signals
accept
use_addr
data_buf_addr
Write Command Signals
wr_data
wr_data_addr
wr_data_mask
wr_data_en
wr_data_offset
Read Command Signals
rd_data
rd_data_addr
rd_data_en
rd_data_offset
Native Interface Maintenance Command Signals
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
Clocking Architecture
Internal (FPGA) Logic Clock
Write Path (Output) I/O Logic Clock
Read Path (Input) I/O Logic Clock
IDELAY Reference Clock
Memory Controller
Bank Machines
Rank Machines
Column Machine
Arbitration Block
Reordering
Precharge Policy
PHY
Overall PHY Architecture
Memory Initialization and Calibration Sequence
I/O Architecture
PHY Control Block
Command Path
Datapath
Calibration and Initialization Stages
Memory Initialization
Read Leveling
Read Valid Calibration
PRBS Read Leveling
Phase Detector
Memory Controller to PHY Interface
Designing with the Core
Interfacing to the Core
User Interface
Command Path
Write Path
Read Path
User ZQ
Native Interface
User ZQ
Customizing the Core
Design Guidelines
LPDDR2 SDRAM
Design Rules
Pin Assignments
Bank and Pin Selection Guides for LPDDR2 Designs
Bank Sharing Among Controllers
Pin Swapping
Internal VREF
System Clock, MMCM Location, and Constraints
Configuration
Termination
I/O Standards
Trace Lengths
Clocking
Input Clock Guidelines
Sharing sys_clk between Controllers
Information on Sharing BUFG Clock (phy_clk)
Information on Sync_Pulse
LPDDR2 Pinout Examples
CLOCK_DEDICATED_ROUTE Constraints
Syetem Clock
Reference Clock
Multicontroller Design
Introduction
Using MIG in the Vivado Design Suite
Customizing and Generating the Core
Multiple Controllers
Creating 7 Series FPGA Multicontroller Block Design
Memory Selection
FPGA Options
Extended FPGA Options Page
System Clock Pins Selection
System Clock Sharing
Vivado Integrated Design Flow for MIG
Directory Structure
Upgrading the ISE/CORE Generator MIG Core in Vivado
General Memory Routing Guidelines
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices