Theoretical Bandwidth - Theoretical Bandwidth - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)
Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English
The following tables provide a basic introduction of relative performance capabilities between various programmable interfaces, DMA, and memory controllers. The bandwidth are calculated as the interface width multiplied by a typical clock rate, not including any protocol overhead.
Table 1. Theoretical Bandwidth of PS-PL and PS Memory Interfaces
Interface Type Bus Width (bits) IF Clock (MHz) Read Bandwidth (MB/s) Write Bandwidth (MB/s) R+W Bandwidth (MB/s) Number of Interfaces Total Bandwidth (MB/s)
General Purpose AXI PS Slave 32 150 600 600 1,200 2 2,400
General Purpose AXI PS Master 32 150 600 600 1,200 2 2,400
High Performance (AFI) AXI_HP PS Slave 64 150 1,200 1,200 2,400 4 9,600
AXI _ACP PS Slave 64 150 1,200 1,200 2,400 1 2,400
DDR External Memory 32 1,066 4,264 4,264 4,264 1 4,264
OCM Internal Memory 64 222 1,779 1,779 3,557 1 3,557
Table 2. Theoretical Bandwidth of PS DMA Controllers
DMA Type IF Width (Bits) IF Clock (MHz) Read BW (MB/s) Write BW (MB/s) R+W BW (MB/s) Number of Interfaces Total Bandwidth (MB/s)
DMAC Arm PL310 64 222 1,776 1,776 3,552 1 3,552
Gigabit Ethernet PS Master 4 250 125 125 250 2 500
USB PS Master 8 60 60 60 60 2 120
SD PS Master 4 50 25 25 25 2 50
Table 3. Theoretical Bandwidth of PS Interconnect
Interconnect Clock Domain IF Width (Bits) IF Clock (MHz) Read BW (MB/S) Read BW (MB/S) R+W BW (MB/s)
Central Interconnect CPU_2x 64 222 1,776 1,776 3,552
Masters CPU_1x 32 111 444 444 888
Slaves CPU_1x 32 111 444 444 888
Master Interconnect CPU_2x 32 222 888 888 1,776
Slave Interconnect CPU_2x 32 222 888 888 1,776
Memory Interconnect DDR_2x 64 355 2,840 2,840 5,680

A few performance insights can be inferred from these relative throughputs:

  • The OCM or DDR memories are not able to be fully used by a single master, except if a low DDR clock rate is used. For example, DDR read bandwidth is limited to 2,840 MB/s on a particular port by the memory interconnect.
  • The interconnect generally provides enough bandwidth to sustain access to the memory devices.