SLCR Registers - SLCR Registers - 1.15 English

The System-Level Control registers (SLCR) consist of various registers that are used to control the PS behavior. These registers are accessible via the central interconnect using load and store instructions. The detailed descriptions for each register can be found in Register Details. A summary of the SLCR registers with their base addresses is shown in the following table.

Table 1. SLCR Register Map
Register Base Address	Description	Reference
`F800_0000`	SLCR write protection lock and security
`F800_0100`	Clock control and status	See Clocks
`F800_0200`	Reset control and status	See Reset System
`F800_0300`	APU control	See Application Processing Unit
`F800_0400`	TrustZone control	See Programming ARM TrustZone Architecture on the Xilinx Zynq-7000 All Programmable SoC User Guide (UG1019)
`F800_0500`	CoreSight SoC debug control	See System Test and Debug
`F800_0600`	DDR DRAM controller	See DDR Memory Controller
`F800_0700`	MIO pin configuration	See Signals, Interfaces, and Pins
`F800_0800`	MIO parallel access	See Signals, Interfaces, and Pins
`F800_0900`	Miscellaneous control	See On-Chip Memory (OCM)
`F800_0A00`	On-chip memory (OCM) control	See On-Chip Memory (OCM)
`F800_0B00`	I/O buffers for MIO pins (GPIOB) and DDR pins (DDRIOB)	See Signals, Interfaces, and Pins

SLCR Registers - SLCR Registers - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)