Register reg15_debug_ctrl Details - Register reg15_debug_ctrl Details - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English
Field Name Bits Type Reset Value Description
reserved 31:3 waz,raz 0x0 reserved
SPNIDEN 2 rw 0x0 Reads value of SPNIDEN input.
DWB 1 rw 0x0

DWB: Disable write-back, force WT 0 = Enable write-back behavior. This is the default.

1 = Force write-through behavior

DCL 0 rw 0x0

DCL: Disable cache linefill 0 = Enable cache linefills. This is the default.

1 = Disable cache linefills.