| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
|
XNANDPS_OPMODE_ADDRESS_MATCH_MASK (OPMODE_ADDRESS_MATCH) |
31:24 | ro | 0xE4 | see 0x120 |
|
XNANDPS_OPMODE_ADDRESS_MASK (OPMODE_ADDRESS) |
23:16 | ro | 0xFE | see 0x120 |
|
XNANDPS_OPMODE_BURST_ALIGN_MASK (OPMODE_BURST_ALIGN) |
15:13 | ro | 0x0 | reserved |
|
XNANDPS_OPMODE_BLS_MASK (OPMODE_BLS) |
12 | ro | 0x0 | reserved |
|
XNANDPS_OPMODE_ADV_MASK (OPMODE_ADV) |
11 | ro | 0x1 | reserved |
|
XNANDPS_OPMODE_BAA_MASK (OPMODE_BAA) |
10 | ro | 0x0 |
The memory uses the burst address advance signal, baa_n, when set. For a NAND memory interface, this bit is reserved. |
|
XNANDPS_OPMODE_WR_BL_MASK (OPMODE_WR_BL) |
9:7 | ro | 0x0 | Selects the write burst lengths, see SET_OPMODE register. |
|
XNANDPS_OPMODE_WR_SYNC_MASK (OPMODE_WR_SYNC) |
6 | ro | 0x0 | SRAM/NOR interface operates in asynchronous mode |
|
XNANDPS_OPMODE_RD_BL_MASK (OPMODE_RD_BL) |
5:3 | ro | 0x0 | Select memory burst lengths, see SET_OPMODE Register. |
|
XNANDPS_OPMODE_RD_SYNC_MASK (OPMODE_RD_SYNC) |
2 | ro | 0x0 | reserved |
|
XNANDPS_OPMODE_MW_MASK (OPMODE_MW) |
1:0 | ro | 0x0 | Data bus width (8 or 16), see SET_OPMODE register. |