| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| reg_ddrc_dfi_t_wlmrd | 25:16 | rw | 0x28 |
DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. |
| reg_ddrc_rdlvl_rr | 15:8 | rw | 0x40 |
DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. |
| reg_ddrc_wrlvl_ww | 7:0 | rw | 0x27 |
DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) |