Register XUSBPS_EPRDY_OFFSET Details - Register XUSBPS_EPRDY_OFFSET Details - 1.15 English - UG585

For each endpoint, there is one buffer ready status (ENDPTSTAT) bit for the TX buffer and one bit for RX buffer.

An ENDPTSTAT bit is set to a 1 by the hardware in a response to receiving an EP prime command (write 1 to usb.ENDPTPRIME regsiter). There will always be a delay between writing a 1 to a usb.ENDPTPRIME register bit and the ENDPTSTAT bit asserting to indicate ready. This delay time varies based upon the current USB traffic and the number of bits in the usb.ENDPTPRIME register that transition from 0 to 1.

An ENDPTSTAT bit is cleared in one of three ways: by a USB reset, by the DMA engine hardware, or by a flush command using the usb.ENDPTFLUSH register.