This write only register is used to enable interrupts. When any bit is written high, the corresponding interrupt is enabled. Writing a low to any bit has no effect.
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| reserved | 31:13 | ro | 0x0 | Reserved, read as zero, ignored on write. |
| TOVR | 12 | wo | 0x0 |
Transmitter FIFO Overflow interrupt: 0: no affect 1: enable (clears mask = 0) |
| TNFUL | 11 | wo | 0x0 |
Transmitter FIFO Nearly Full interrupt: 0: no affect 1: enable (clears mask = 0) |
| TTRIG | 10 | wo | 0x0 |
Transmitter FIFO Trigger interrupt: 0: disable 1: enable |
|
XUARTPS_IXR_DMS (IXR_DMS) |
9 | wo | 0x0 |
Delta Modem Status Indicator interrupt: 0: no affect 1: enable (clears mask = 0) |
|
XUARTPS_IXR_TOUT (IXR_TOUT) |
8 | wo | 0x0 |
Receiver Timeout Error interrupt: 0: no affect 1: enable (clears mask = 0) |
|
XUARTPS_IXR_PARITY (IXR_PARITY) |
7 | wo | 0x0 |
Receiver Parity Error interrupt: 0: disable 1: enable |
|
XUARTPS_IXR_FRAMING (IXR_FRAMING) |
6 | wo | 0x0 |
Receiver Framing Error interrupt: 0: no affect 1: enable (clears mask = 0) |
|
XUARTPS_IXR_OVER (IXR_OVER) |
5 | wo | 0x0 |
Receiver Overflow Error interrupt: 0: no affect 1: enable (clears mask = 0) |
|
XUARTPS_IXR_TXFULL (IXR_TXFULL) |
4 | wo | 0x0 |
Transmitter FIFO Full interrupt: 0: no affect 1: enable (clears mask = 0) |
|
XUARTPS_IXR_TXEMPTY (IXR_TXEMPTY) |
3 | wo | 0x0 |
Transmitter FIFO Empty interrupt: 0: disable 1: enable |
|
XUARTPS_IXR_RXFULL (IXR_RXFULL) |
2 | wo | 0x0 |
Receiver FIFO Full interrupt: 0: no affect 1: enable (clears mask = 0) |
|
XUARTPS_IXR_RXEMPTY (IXR_RXEMPTY) |
1 | wo | 0x0 |
Receiver FIFO Empty interrupt: 0: no affect 1: enable (clears mask = 0) |
|
XUARTPS_IXR_RXOVR (IXR_RXOVR) |
0 | wo | 0x0 |
Receiver FIFO Trigger interrupt: 0: no affect 1: enable (clears mask = 0) |