Register XEMACPS_LADDR4L_OFFSET Details - Register XEMACPS_LADDR4L_OFFSET Details - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English
Field Name Bits Type Reset Value Description
  31:0 rw 0x0 Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.