| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| DMASEV_active | 31:0 | sro,nssraz,nsnsro | 0x0 |
Raw status of the event or interrupt state. There are sixteen possible event settings [15:0] and eight possible interrupts [7:0]: 0: Inactive 1: Active Note: When the DMAC executes a DMASEV N instruction to send event N, the INTEN Register controls whether the DMAC: signals an interrupt using the appropriate irq sends the event to all of the threads. Reserved |