Register XCANPS_BTR_OFFSET Details - Register XCANPS_BTR_OFFSET Details - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

The Bit Timing Register (BTR) specifies the bits needed to configure bit time. Specifically, the Propagation Segment, Phase segment 1, Phase segment 2, and Synchronization Jump Width (as defined in CAN 2.0A, CAN 2.0B and ISO 11891-1) are written to the BTR. The actual value of each of these fields is one more than the value written to this register.

Field Name Bits Type Reset Value Description
reserved 31:9 rw 0x0 Reserved

XCANPS_BTR_SJW_MASK

(SJW)

8:7 rw 0x0

Synchronization Jump Width

Indicates the Synchronization Jump Width as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.

XCANPS_BTR_TS2_MASK

(TS2)

6:4 rw 0x0

Time Segment 2

Indicates Phase Segment 2 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.

XCANPS_BTR_TS1_MASK

(TS1)

3:0 rw 0x0

Time Segment 1

Indicates the Sum of Propagation Segment and Phase Segment 1 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.