Register Overview - Register Overview - 1.15 English

The following table provides an overview of the DMA Controller registers.

Table 1. DMAC Register Overview
Function	Register Name	Overview
DMAC Control	dmac.XDMAPS_DS dmac.XDMAPS_DPC	Provides the security state and the program counter.
Interrupts and Events	dmac.INT_EVENT_RIS dmac.INTCLR dmac.INTEN dmac.INTMIS	Enables/disables the interrupt detection, mask interrupt sent to the interrupt controller, and reads raw interrupt status.
Fault Status and Type	dmac.FSRD dmac.FSRC dmac.FTRD dmac.FTR{7:0}	Provides the fault status and type for the manager and the channels.
Channel Thread Status	dmac.CPC{7:0} dmac.CSR{7:0} dmac.SAR{7:0} dmac.DAR{7:0} dmac.CCR{7:0} dmac.LC0_{7:0} dmac.LC1_{7:0}	These registers provide the status of the DMA channel threads.
Debug	dmac.DBGSTATUS dmac.DBGCMD dmac.DBGINST{1,0}	These registers enable the user to send instructions to a channel thread.
IP Configuration	dmac.XDMAPS_CR{4:0} dmac.XDMAPS_CRDN	These registers enable system firmware to discover the hardwired configuration of the DMAC
Watchdog	dmac.WD	Controls how the DMAC responds when it detects a lock-up condition.
System-level	slcr.DMAC_RST_CTRL slcr.TZ_DMAC_NS slcr.TZ_DMA_IRQ_NS slcr.TZ_DMAC_PERIPH_NS slcr.DMAC_RAM slcr.APER_CLK_CTRL	Control reset, clock, and security state.

Register Overview - Register Overview - 1.15 English - UG585