An overview of the PS-XADC Interface control registers is shown in the following table. Register bit details are provided in Register Details. Refer to the XADC Register Interface section of the 7 Series FPGAs and Zynq 7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) for register details of the XADC.
Note: After power-up (refer to the Zynq 7000 SoC data sheet for the proper voltage sequencing),
PS-to-PL voltage shifters are automatically enabled. The PL must be powered-up to
access the PS-XADC interface registers, but the PL does not need to be configured to
access the registers.
The following table shows an overview of XADC Interface registers.
| Function | Mnemonic | Description | Type |
|---|---|---|---|
| Configuration | devcfg.XADCIF_CFG | Configuration: Enable, FIFO threshold, frequency ratio, and launch edge. | Read/Write |
| devcfg.XADCIF_MCTL | XADC Interface Misc. Control register | Read/Write | |
| Interrupts | devcfg.XADCIF_INT_STS | XADC Interface Interrupt Status register |
Read, Write 1 to clear |
| devcfg.XADCIF_INT_MASK | XADC Interface Interrupt Mask register | Read/Write | |
| devcfg.XADCIF_MSTS | XADC Interface Misc. Status register | Read | |
| Command and Read Data FIFOs | devcfg.XADCIF_CMDFIFO | XADC Interface Command FIFO | Write |
| devcfg.XADCIF_RDFIFO | XADC Interface Read Data FIFO | Read |