Register Normal_interrupt_status_Error_interrupt_status Details - Register Normal_interrupt_status_Error_interrupt_status Details - 1.15 English - UG585

Occurs when ATA command termination has occurred due to an error condition the device has encountered.

0 - no error

1 - error

Occurs when detecting ERROR in m_hresp(dma transaction)

0 - no error

1 - error

This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.

1- Error

0 -No error

Occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1. This bit is set to 1 also when Auto CMD12 is not executed due to the previous command error.

0 - No Error

1 - Error

By setting the SD Bus Power bit in the Power Control Register, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function.

0 - No Error

1 - Power Fail

Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status.

0 - No Error

1 - Error

Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than '010'.

0 - No Error

1 - Error

Occurs when detecting one of following timeout conditions.

1. Busy Timeout for R1b, R5b type.

2. Busy Timeout after Write CRC status

3. Write CRC status Timeout

4. Read Data Timeout

0 - No Error

1 - Timeout

Occurs if a Command Index error occurs in the Command Response.

0 - No Error

1 - Error

Occurs when detecting that the end bit of a command response is 0.

0 - No Error

1 - End Bit Error Generated

Command CRC Error is generated in two cases.

1. If a response is returned and the Command Timeout Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response

2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict.

0 - No Error

1 - CRC Error Generated

Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC.

0 - No Error

1 - Timeout

If any of the bits in the Error Interrupt Status Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first.

0 - No Error.

1 - Error.

This status is set if the boot operation get terminated

0 - Boot operation is not terminated.

1 - Boot operation is terminated

This status is set if the boot acknowledge is received from device.

0 - Boot ack is not received.

1 - Boot ack is received.

Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system. When this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again.

0 - No Card Interrupt

1 - Generate Card Interrupt

This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.

Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.

0 - Card State Stable or Debouncing

1 - Card Removed

This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.

Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.

0 - Card State Stable or Debouncing

1 - Card Inserted

This status is set if the Buffer Read Enable changes from 0 to 1.

0 - Not Ready to read Buffer.

1 - Ready to read Buffer.

This status is set if the Buffer Write Enable changes from 0 to 1.

0 - Not Ready to Write Buffer.

1 - Ready to Write Buffer.

This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size register.

0 - No DMA Interrupt

1 - DMA Interrupt is Generated

If the Stop At Block Gap Request in the Block

Gap Control Register is set, this bit is set. Read Transaction:

This bit is set at the falling edge of the DAT Line Active Status (When the transaction is stopped at SD Bus timing. The Read Wait must be supported in order to use this function).

Write Transaction:

This bit is set at the falling edge of Write Transfer Active Status (After getting CRC status at SD Bus timing).

0 - No Block Gap Event

1 - Transaction stopped at Block Gap

This bit is set when a read / write transaction is completed.

Read Transaction:

This bit is set at the falling edge of Read Transfer Active Status.

There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (After the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request in the Block Gap Control Register (After valid data has been read to the Host System).

Write Transaction:

This bit is set at the falling edge of the DAT

Line Active Status.

There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed. (After valid data is written to the SD card and the busy signal is released).

• Transfer Complete has higher priority than Data Timeout Error. If both bits are set to 1, the data transfer can be considered complete

0 - No Data Transfer Complete

1 - Data Transfer Complete

This bit is set when get the end bit of the command response (Except Auto CMD12).

• Command Timeout Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly.

0 - No Command Complete

1 - Command Complete