Register MIO_PIN_46 Details - Register MIO_PIN_46 Details - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English
Field Name Bits Type Reset Value Description
reserved 31:14 rw 0x0 reserved
DisableRcvr 13 rw 0x0 Operates the same as MIO_PIN_00[DisableRcvr]
PULLUP 12 rw 0x1 Operates the same as MIO_PIN_00[PULLUP]
IO_Type 11:9 rw 0x3 Operates the same as MIO_PIN_00[IO_Type]
Speed 8 rw 0x0 Operates the same as MIO_PIN_00[Speed]
L3_SEL 7:5 rw 0x0

Level 3 Mux Select

000: GPIO 46 (bank 1), Input/Output

001: CAN 0 Rx, Input

010: I2C 0 Serial Clock, Input/Ouput

011: PJTAG TDI, Input

100: SDIO 1 IO Bit 0, Input/Output

101: SPI 1 MOSI, Input/Output

110: reserved

111: UART 0 RxD, Input

L2_SEL 4:3 rw 0x0

Level 2 Mux Select

00: Level 3 Mux

01: reserved

10: reserved

11: SDIO 0 Power Control, Output

L1_SEL 2 rw 0x0

Level 1 Mux Select

0: Level 2 Mux

1: USB 1 ULPI Data Bit 2, Input/Output

L0_SEL 1 rw 0x0

Level 0 Mux Select

0: Level 1 Mux

1: reserved

TRI_ENABLE 0 rw 0x1 Operates the same as MIO_PIN_00[TRI_ENABLE]