Register Initialization Parameters — 0x0A0 to 0x89C - Register Initialization Parameters — 0x0A0 to 0x89C - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

This region contains 256 pairs of address and data words that can be used to initialize PS registers for the MIO multiplexer, boot device clocks, and other functions before the FSBL/User code is accessed from the boot device; either to copy the image to the OCM or to execute-in-place. The register writes are commonly used to optimize the boot device interface and set its clock frequency to maximize performance.

A register initialization pair appears as two 32-bit words, first a register address, then a register write value. Register initializations can be in any order, and the same register can be initialized with different values as many times as desired. The register initialization is performed prior to copying the FSBL/User code so the user can modify the default reset register values to reduce the time to access the code and process it.

The BootROM stops processing the Register Initialization list when either the address register = 0xFFFF_FFFF or the end of the list (256 address/write data pairs).

Usage of the register initialization parameters are explained in the “Register Initialization to Optimize Boot Times” section of BootROM Performance.

Restricted Addresses

The register address space for the Register Initialization address-data writes is restricted. Register addresses outside of the allowed address range cause the BootROM to lockdown the system and generate error code 0x2111. The allowed register accesses depend on the boot mode and are listed in the following table.

These restrictions are enforced by the BootROM. They do not apply when the FSBL/User code begins to execute. The BootROM screens the register initialization writes and disallows certain addresses from being accessed.

Table 1. BootROM Accessible Address Ranges for Register Initialization
Control Registers Non-Secure Boot Mode Secure Boot Mode
Ranges Exceptions to Range 1
UART 1 E000_1000 to E000_1FFC ~ No
Quad-SPI E000_D000 to E000_DFFC ~ No
SMC E000_E000 to E000_EFFC ~ No
SDIO 0 E010_0004 to E010_0FFC E010_0058 No
DDR Memory F800_6000 to F800_6FFC ~ No
SLCR registers
PLL, Peripheral, AMBA and CPU clock controls F800_0100 to F800_0234

Reserved: F800_01B0

PS Reset Ctrl: F800_0200

PLL, Peripheral and PL clock controls:

F800_0100 to F800_01AC

SWDT Reset F800_024C ~
SWDT clock, TZ configuration, PS ID code, DDR configuration, MIO pins, SD card WP/CD routing F800_0304 to F800_0834 ~
Reserved F800_0A00 to F800_0A8C ~
Reserved, GPIO and DDR I/O controls F800_0AB0 to F800_0B74 ~
UART 0, USB, I2C, SPI, CAN, GPIO, GigE, TTC, DMAC, SWDT, DDR, DevC, AXI HP Not accessible Not accessible
  1. The registers in this column are not accessible by the Register Initialization writes.