| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Set | 31:0 | rw | 0x0 |
The ICDISERs provide a Set-enable bit for each interrupt supported by the GIC. Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt to the CPU interfaces. A register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure access. |