The ICDICFR 3 register control the interrupt sensitivity of the Shared Peripheral Interrupts (SPI), IRQ ID #48 to ID #63. This register has two bits per interrupt. This two bit field is either equal to 01 (high-level active) or equal to 11 (rising-edge sensitive). The LSB is always 1 because only one CPU will handle a SPI interrupt, regardless of the number of CPUs targeted.
Refer to Shared Peripheral Interrupts (SPI) for the required sensitivity type for the SPI interrupts. The SPI interrupts must match the expected sensitivity. Interrupts from the PL may be high-level or rising edge sensitive; this must be coordinated with the PL hardware and software.
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| config_63 | 31:30 | rw | 0x1 |
Configuration for interrupt ID#63 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_62 | 29:28 | rw | 0x1 |
Configuration for interrupt ID#62 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_61 | 27:26 | rw | 0x1 |
Configuration for interrupt ID#61 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_60 | 25:24 | rw | 0x1 |
Configuration for interrupt ID#60 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_59 | 23:22 | rw | 0x1 |
Configuration for interrupt ID#59 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_58 | 21:20 | rw | 0x1 |
Configuration for interrupt ID#58 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_57 | 19:18 | rw | 0x1 |
Configuration for interrupt ID#57 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_56 | 17:16 | rw | 0x1 |
Configuration for interrupt ID#56 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_55 | 15:14 | rw | 0x1 |
Configuration for interrupt ID#55 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_54 | 13:12 | rw | 0x1 |
Configuration for interrupt ID#54 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_53 | 11:10 | rw | 0x1 |
Configuration for interrupt ID#53 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_52 | 9:8 | rw | 0x1 |
Configuration for interrupt ID#52 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_51 | 7:6 | rw | 0x1 |
Configuration for interrupt ID#51 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_50 | 5:4 | rw | 0x1 |
Configuration for interrupt ID#50 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_49 | 3:2 | rw | 0x1 |
Configuration for interrupt ID#49 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |
| config_48 | 1:0 | rw | 0x1 |
Configuration for interrupt ID#48 01: high-level active 11: rising-edge The lower bit is read-only and is always 1. |