Register ENDPTCTRL1 to ENDPTCTRL11 Details - Register ENDPTCTRL1 to ENDPTCTRL11 Details - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English
Field Name Bits Type Reset Value Description
TXE 23 rw 0x0

TX Endpoint Enable.

0: disable.

1: enable.

Enable an Endpoing after it has been configured.

TXR 22 rw 0x0

TX Data Toggle Reset.

Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.

TXI 21 ro 0x0

TX Data Toggle Inhibit. (testing)

0: PID Sequencing enabled

1: PID Sequencing disabled

reserved 20 ro 0x0 reserved
TXT 19:18 rw 0x0

TX Endpoint Type control.

00: Control

01: Isochronous

10: Bulk

11: Interrupt

TXD 17 rw 0x0

TX Endpoint Data datapath.

0: dual-port memory buffer with a DMA Engine. Always write a 0.

TXS 16 rw 0x0

TX Endpoint Stall.

0: Normal operation.

1: Force Stall handshake.

  • Refer to the ENDPTCTRL 0 register description for more description.
reserved 15:8 ro 0x0 reserved
RXE 7 rw 0x0

RX Endpoint Enable

0: Disable

1: Enable

Enable an Endpoing after it has been configured.

RXR 6 rw 0x0

RX Data Toggle Reset.

Write '1' will reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device.

RXI 5 rw 0x0

RX Data Toggle Inhibit.

0: PID Sequencing enabled

1: PID Sequencing disabled

reserved 4 rw 0x0 reserved
RXT 3:2 rw 0x0

RX Endpoint Type.

00: Control

01: Isochronous

10: Bulk

11: Interrupt

RXD 1 rw 0x0

RX Endpoint Data datapath.

0: dual-port memory buffer with a DMA Engine. Always write a 0.

RXS 0 rw 0x0

RX Endpoint Stall.

0: Normal operation.

1: Force Stall handshake.

  • Refer to the ENDPTCTRL 0 register description for more description.