| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| reg_ddrc_t_rcd | 31:28 | rw | 0x8 | tRCD - AL Minimum time from activate to read or write command to same bank. Min value for this is 1. AL = Additive Latency. DRAM Related. |
| reg_ddrc_rd2pre | 27:23 | rw | 0x6 |
Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. |
| reg_ddrc_pad_pd | 22:20 | rw | 0x0 |
If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. |
| reg_ddrc_t_xp | 19:15 | rw | 0x2 | tXP: Minimum time after power down exit to any operation. DRAM related. |
| reg_ddrc_wr2rd | 14:10 | rw | 0x16 |
Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. |
| reg_ddrc_rd2wr | 9:5 | rw | 0x8 |
Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. |
| reg_ddrc_write_latency | 4:0 | rw | 0x4 |
Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where, WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 |