Programming Guide for the DRP Interface - Programming Guide for the DRP Interface - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

The XADC can also be accessed by instantiating an AMD LogiCOREā„¢ AXI XADC bridge in the PL. This method provides more powerful features and easy access to all XADC registers and signals using a register read/write programming model for microprocessors.